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Technique for forming gapless shallow channel insulation area by subatmospheric CVD method

A technology of atmospheric pressure chemical vapor phase and insulating area, which is applied in the manufacture of electrical components, semiconductor/solid state devices, circuits, etc., and can solve problems such as fast wet etching rate, erosion in cleaning steps, short circuit of polysilicon lines, etc.

Active Publication Date: 2008-07-02
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the aforementioned ozone-assisted subatmospheric pressure chemical vapor deposition technology still has many shortcomings in practical application and needs to be further overcome and improved.
The silicon-oxygen film deposited by the existing ozone-assisted sub-atmospheric pressure chemical vapor deposition technology itself will shrink at high temperature, for example, after 30 minutes at 1050 ° C, the shrinkage will be as high as about 7%, and the SACVD silicon-oxygen film Thin films also have poorer properties, e.g. faster wet etch rates
In addition, if figure 1 As shown, another more serious problem of the ozone-assisted sub-atmospheric pressure chemical vapor deposition technology is that the growth characteristic of the sub-atmospheric pressure chemical vapor deposition film is mainly from the sidewall 22 of the ditch 20 to the middle to fill the ditch, therefore, eventually will A tight seam (seam) 50 is formed in the middle of the trench 20 of the substrate 10, and the seam defect 50 cannot be removed by conventional nitrogen environment annealing, and is easily corroded by subsequent cleaning steps, resulting in the formation of communication trenches and Polysilicon line short circuit and other problems

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  • Technique for forming gapless shallow channel insulation area by subatmospheric CVD method
  • Technique for forming gapless shallow channel insulation area by subatmospheric CVD method
  • Technique for forming gapless shallow channel insulation area by subatmospheric CVD method

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Embodiment Construction

[0019] In order to further clearly illustrate the content of the process of forming the seamless shallow trench insulation region by the sub-atmospheric pressure chemical vapor deposition technology of the present invention, the following refers to Figures 2 to 6 Describe its manufacturing process and steps in detail, among which Figures 2 to 5 Shown is a schematic cross-sectional view of a process for forming a seamless shallow trench isolation region according to a preferred embodiment of the present invention, Image 6 A flowchart of a process for forming seamless STI regions according to a preferred embodiment of the present invention.

[0020] First, if figure 2 As shown, a pad oxide layer 32 with a thickness of about 30 angstroms to 200 angstroms is covered on a semiconductor substrate 10, such as a silicon substrate. The pad oxide layer 32 can be formed by chemical vapor deposition or thermal oxidation growth. Subsequently, a pad silicon nitride layer 34 with a th...

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Abstract

The invention discloses a trench insulation area process, firstly forming an isolation trench in a semiconductor substrate; making SACVD (selected area chemical vapor deposition) to deposit a silicon oxide layer on the semiconductor substrate and making the silicon oxide fill the isolation trench, where the silicon oxide layer forms a joint in the isolation trench; making a low-temperature vapor annealing process to eliminate the joint in hydrogen / oxygen gas; and finally making a high temperature annealing process to compact the silicon oxide layer in inert gas with a temperature higher than 900 deg.C.

Description

technical field [0001] The present invention relates to the manufacture of semiconductor integrated circuits, in particular to a process for forming a seamless shallow trench isolation region by using sub-atmospheric pressure chemical vapor deposition (SACVD) technology. Background technique [0002] In recent years, with the continuous shrinking of the design line width of the semiconductor process, the trench isolation or shallow trench isolation (STI) process, which is implemented on the surface of the semiconductor substrate and used to effectively isolate the device electrically, has become more and more important. It is an increasingly important topic, and how to effectively fill the increasingly narrow insulation trenches has become a major challenge in this technical field. [0003] The traditional shallow trench isolation process is to first use the chemical vapor deposition (chemical vapor deposition, CVD) method to fill the dielectric layer in the insulating trenc...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/31
Inventor 许绍达陈能国蔡腾群
Owner UNITED MICROELECTRONICS CORP