Chip testing method and related devices

Abstract

The related chip testing method comprises: to test dual-direction high-speed bus, transmitting the testing signal into chip through low-speed bus, letting the high-speed bus transmission mechanism to send the testing signal to the high-speed bus interface, and also letting the receiving mechanism form an inner loop and back transmit the information by low-speed bus. Thereby, this invention can save testing cost.

Description

technical field [0001] The invention relates to a chip testing method and a related device, in particular to a chip testing method and a related device with a high-speed bus interface tested in a low-speed testing environment. Background technique [0002] In an electronic system, different electronic circuits / chips exchange information with each other through a bus, so that the electronic circuits / chips can coordinate their operations and integrate their respective functions to achieve the overall function of the electronic system. For example, in a computer system, the central processing unit is bridged to other peripheral devices (such as hard drives, optical drives, display cards, etc.) They will be connected to each other by a bus, so that the above-mentioned electronic circuits / chips can be integrated and operated. Of course, in the modern information society that emphasizes efficiency, the performance requirements for electronic systems are also increasing. In order...

AI Technical Summary

Problems solved by technology

However, in the traditional technology, because the tester can only sample the data indication signal at a specific time point, it cannot judge the trigger edge position of the data indication signal, so it is impossible to know whether the timing relationship between the data indication signal and the data signal is correct

In other words, the test results of traditional technology cannot completely and truly show the input and output performance of the chip

Images