Transistor, memory cell and method of manufacturing a transistor

Abstract

A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source / drain regions, a channel connecting the first and second source / drain regions, a gate electrode for controlling an electrical current flowing between the first and second source / drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source / drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source / drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.

Description

technical field [0001] The present invention relates to transistors, memory cells of DRAM (Dynamic Random Access) memory and methods of making such transistors. Background technique [0002] A memory cell of a dynamic random access memory (DRAM) includes a storage capacitor for storing charge representing stored information, and an access transistor for addressing the storage capacitor. The access transistor includes first and second source / drain regions, a conductive channel connecting the first and second source / drain regions, and a gate electrode controlling current flow between the first and second source / drain regions. The transistor is usually formed in a semiconductor substrate, specifically a silicon substrate. Information stored in the storage capacitor is read or written through the address access transistor. There is a lower boundary of the channel length of the access transistor, below which the isolation characteristic of the access transistor in the non-addre...

AI Technical Summary

Problems solved by technology

There is a lower boundary of the channel length of the access transistor below which the isolation characteristics of the access transistor in the non-addressed state are insufficient

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