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Improved electrostatic discharge protecting circuit

An electrostatic discharge protection and electrostatic discharge technology, which is applied to emergency protection circuit devices, emergency protection circuit devices for limiting overcurrent/overvoltage, circuits, etc., can solve problems such as increasing chip size, and achieve size saving and simplification. The effect of the design

Inactive Publication Date: 2007-09-19
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But usually an additional detection circuit needs to be added to the substrate driver circuit, which will increase the size of the chip

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] The substrate-driven scheme shown in Figure 3 can be simplified to be compatible with standard CMOS processes. If the substrate is connected to the gate using the ESD MOS shown in Figure 4, no detection circuit is required.

[0039] Similar to the gate drive structure, when the ESD negative pulse from VM to VDD occurs, the body of the MP will be coupled low (relative to the MP) due to the existence of the large parasitic capacitance Cgd of the MP (the capacitance between the gate and the drain of the MP). In terms of the voltage of VDD, it is lower than the voltage of VDD and closer to the voltage of VM). At the same time, a current flowing out of the MP substrate is generated at the substrate of the MP. This substrate bias current will flow through the bulk resistance and create a voltage drop across it. If the voltage drop is greater than the V required to trigger the parasitic PNP BE Positive bias value, the parasitic PNP will be triggered, and the static electric...

Embodiment 2

[0047] On the basis of the ESD protection circuit 1 shown in Figure 4, a capacitor C is added between the gate of MP and VM, as shown in Figure 5, to obtain the ESD protection circuit 2 for negative input voltage pins.

[0048] In the ESD protection circuit 2, on the one hand, the increase of C is the same as the prior art (Fig. 1), which will increase the coupling voltage between the drain and the gate of MP during electrostatic discharge; When a fast ESD pulse voltage is applied, the capacitor C needs to be charged first (the initial voltage of the capacitor C is zero), a part of the charging current will flow out from the N well of MP, and the increase of C will also increase the output from the N well of MP. The outflow current, the latter can enhance the ESD discharge capability of the MP tube.

[0049] The ESD protection circuit 2 works the same as the ESD protection circuit 1 when electrostatic discharge occurs, except that the capacitor C will further enhance the disch...

Embodiment 3

[0054] FIG. 6 shows the ESD protection circuit 3 for common input voltage pins according to Embodiment 2 of the present invention, including resistors R1 and R2 , NMOS transistor MN and diode D. One end of resistor R1 is connected to the gate of MN, the other end is grounded to GND; the drain of MN is connected to a voltage VI, the source is grounded to GND, the gate is connected to the substrate, VI is connected to the internal circuit through the resistor R2, and the positive electrode of diode D Ground GND, the negative pole is connected to voltage VI, and an ESD protection circuit is connected between the power supply and the ground.

[0055] When a positive ESD pulse is generated from VI to GND, the static electricity will be discharged through the reverse breakdown of MN; when a negative ESD pulse is generated from VI to GND, the static electricity will be discharged through the forward conduction of the diode D. When a positive ESD pulse is generated from VI to VDD, the...

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Abstract

The invention provides an improved static discharge protection circuit, which provides a static discharge route for a first node to a second node when static voltage generates between the first node and the second node, and which includes a PMOS transistor, a resistance R1, a diode D, wherein the drain of the PMOS transistor is connected to the first node, and the source of the same is connected to the second node, and the grid of the same is connected to the second node through the resistance R1, and the positive pole is connected to the first node, and the negative pole is connected to the second node, and the substrate of the PMOS transistor is connected to its grid; the PMOS transistor can substituted by a NMOS transistor, in this manner, the positive pole of the diode D is connected to the second node, and the negative pole is connected to the first node, and the substrate of the NMOS transistor is connected to its grid. Comparing with current technology, the provided circuit eliminates complicated detecting circuit, and the NMOS transistor and PMOS transistor can be made by using standard procedure but not complicated N-well procedure.

Description

technical field [0001] The invention relates to an electrostatic discharge protection circuit. Background technique [0002] Most ESD protection circuits are designed so that they discharge through the ground pins, which makes it easy to add ESD devices between other pins and the ground pins. However, conventional ESD devices cannot be added to pins that have a negative voltage to ground because this would create a parasitic P-N junction between the ground pin and the negative voltage pin in the ESD device. During normal operation, this parasitic P-N junction is forward biased, resulting in leakage current. In integrated circuits (ICs), it is generally forbidden to trigger parasitic PNP transistors and large leakage currents to prevent circuit failure or even damage. Even if this large leakage current is acceptable, the voltage at this pin will still forward bias the diode, so the voltage at this pin will be clamped to not be lower than the forward voltage drop of the diod...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02H9/00H01L23/60
CPCH01L27/0266
Inventor 王钊尹航
Owner WUXI ZGMICRO ELECTRONICS CO LTD
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