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A gettering method and a wafer using the same

A technology of wafers and absorbing layers, applied in the field of manufacturing wafers, can solve the problems of expensive, increased distance, and depleted surface area

Inactive Publication Date: 2007-10-03
欧米帝克公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although effective, this method is expensive and requires a considerable number of process steps
It is also possible to diffuse the appropriate element onto the surface of the wafer and use it for lateral absorption techniques, but this again requires additional process steps and consumes surface area
In addition, the absorption efficiency is reduced by increasing the distance from the absorption site

Method used

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  • A gettering method and a wafer using the same
  • A gettering method and a wafer using the same
  • A gettering method and a wafer using the same

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Embodiment Construction

[0053] One of ordinary skill in the art will recognize from the context that the same reference numerals are used for similar structures that are not necessarily the same but may have differences. Components and / or structures in the illustrations are not necessarily drawn to scale and are used for illustrative purposes only.

[0054] The SOI wafers used are circular, and the diameter of said wafers is typically 100, 125, 150, 200 or 300 mm, etc., according to the facts known to those of ordinary skill in the art at the priority date of this document.

[0055] However, as one of ordinary skill in the art would appreciate from reading and understanding the text, such shapes and / or dimensions are not limiting, but are given as examples of wafers. According to one embodiment of the invention, the wafer may have different planar shapes, eg conical, but preferably has a regular shape.

[0056] Irregularly shaped wafers may also be used without departing from the scope of embodiment...

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PUM

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Abstract

It is shown in the invention a method for manufacturing a semiconductor wafer structure with an active layer for impurity removal, which method comprises phases of depositing a first layer on a first wafer surface for providing an active layer, an optional phase of preparation for said first layer for next phase, growing thermal oxide layer on a second wafer, bonding said first and second wafers into a stack, annealing the stack for a crystalline formation in said thermal oxide layer as a second layer, and thinning said first wafer to a pre-determined thickness. The invention concerns also a wafer manufactured according to the method, chip that utilizes such a wafer structure and an electronic device utilizing such a chip.

Description

technical field [0001] The present invention relates generally to the technical field of manufacturing wafers, but more specifically to techniques for controlling impurities in wafer structures, as indicated in the preambles of the independent method claims regarding the method for manufacturing wafer structures. The invention also relates to a wafer structure as indicated in the preamble of the independent claim concerning the wafer. The invention also relates to a chip as indicated in the preamble of the independent claim on the chip. The invention also relates to a semiconductor device as indicated in the preamble of the independent claim relating to the semiconductor device. Background technique [0002] When fabricating semiconductor components on SOI wafers, bulk silicon wafers have different impurity characteristics. In bulk silicon wafers, there are several absorption techniques available that can effectively remove impurities, especially certain metallic elements,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/322H01L21/20H01L21/762H01L21/84
CPCH01L21/3226H01L21/67253H01L21/76256H01L29/762H01L21/322
Inventor 加里·马克南
Owner 欧米帝克公司