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Method and system for determining digital signal duty cycle

A duty cycle, clock signal technology, applied in the field of digital systems, can solve the problems of expensive and damaged components

Active Publication Date: 2010-06-02
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this type of duty cycle analysis can work, it is very expensive
Also, this type of analysis can destroy the element under test

Method used

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  • Method and system for determining digital signal duty cycle
  • Method and system for determining digital signal duty cycle
  • Method and system for determining digital signal duty cycle

Examples

Experimental program
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Embodiment Construction

[0021] figure 1 A duty cycle measurement (DCM) circuit 100 is described for measuring the duty cycle of a digital signal, such as the binary clock signal CLK_TEST present at test input 100A. DCM circuit 100 also includes a calibration input 100B that receives a calibration clock signal CLK_CALIB exhibiting a known duty cycle. DCM circuit 100 also includes an output 100C providing an output voltage VC_OUT including duty cycle information. The VC_OUT value varies with the duty cycle of the clock signal CLK_TEST on test input 100A. In other words, as the duty cycle of the clock signal CLK_TEST on the test input 100A changes, the value of the output voltage VC_OUT on the output 100C changes accordingly. In one embodiment, the output voltage VC_OUT varies inversely or indirectly due to the duty cycle of the input CLK_TEST signal. In other words, as the duty cycle of the input CLK_TEST signal increases, the corresponding VC_OUT decreases. Other embodiments may use direct variati...

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PUM

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Abstract

The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cyclevalues. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data storeto determine the duty cycle to which the test clock signal corresponds.

Description

technical field [0001] The disclosure herein relates generally to digital systems, and more particularly to methods and apparatus for measuring the duty cycle of signals employed by such systems. Background technique [0002] Duty cycle refers to the percentage of time that a digital signal such as a clock signal exhibits a "high" state during a complete signal cycle or period. In older digital systems using relatively low clock speeds, the duty cycle of the reference clock signal is generally not critical to system performance. However, as clock speeds increase, the duty cycle of the reference clock signal can become very important to digital system performance. [0003] When a high-speed clock signal clocks a high-performance processor, the duty cycle of the clock signal plays an important role in the performance of the processor. For example, a processor may access system memory on both the leading and trailing edges of a clock signal pulse. In this case, the memory ac...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R29/00H03L7/00
CPCG01R31/31727
Inventor 齐洁明D·W·博尔斯特勒E·黑卢
Owner INT BUSINESS MASCH CORP