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PCIE apparatus satellite communication method and system

A device communication and device technology, applied in the field of communication, can solve problems such as computer systems not working properly

Inactive Publication Date: 2011-08-03
NEW H3C TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since PCIE supports 64-bit address space, if some PCIE devices need to apply for an address space exceeding 4G, the PCIE device will not work properly in a computer system with a 32-bit architecture

Method used

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  • PCIE apparatus satellite communication method and system
  • PCIE apparatus satellite communication method and system
  • PCIE apparatus satellite communication method and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0046]Step s201, start the operating system of the low-level CPU. The operating system takes a computer system with a 32-bit architecture as an example. The topology is as follows: image 3 As shown, the computer system has 2G memory, the address is 0x00000000~0x8000 0000, Root Complex (root) hangs PCIE bridge A and other PCIE bridges, and PCIE bridge A hangs PCIE device A and PCIE device B.

[0047] During the system startup process, the BIOS allocates an address space of a corresponding size according to the requirements of the device, and configures the address space of PCIE device A as 0xF100 0000 to 0xF200 0000; the address space of PCIE device B as 0xF200 0000 to 0xF300 0000. According to the address routing protocol of PCIE, the address range of PCIE bridge A must cover the address space range of PCIE device A and PCIE device B, that is, 0xF0000000~0xF300 0000, so that PCIE bridge A sends the PCIE packet (the destination address of the packet belongs to 0xF000 0000 to ...

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PUM

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Abstract

The invention discloses a communication method. The method is used in a system comprising a low order CPU and two PCIE devices which claim for a high order address space. The method comprises the steps that: the operation system of the low order CPU is started; the high order address spaces of the two PCIE devices are modified; and the address of a PCIE bridge corresponding to the two PCIE devices is modified, so that the PCIE devices which claim for a high order address space can transmit data through the PCIE bridge. The invention discloses a communication system for the PCIE device. In theembodiment of the invention, the devices which claim for a super large address space (exceeding 4G) can be visited from one to another during a computer system with a 32-bit architecture; and the CPUcan visit a device with a super large address space (exceeding 4G) through a read-write agent during a computer system with a 32-bit architecture.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a PCIE device communication method and system. Background technique [0002] PCI Express is a new generation of high-performance I / O (Input / Output, input / output) interconnection technology, referred to as PCIE, which is widely used in computer platforms as a standard local I / O bus. PCIE has the advantages of high performance, simplified I / O, and hierarchical architecture. [0003] figure 1 It is a typical topology diagram of PCIE bus. PCIE is a Point-to-Point (point-to-point) shared switching architecture. Each device (Endpoint) has its own PCIE bus and is directly connected to the switch (switching device) to establish a Point-to-Point communication method. [0004] The device addressing mode maintains compatibility with the PCI addressing mode, that is, the load-store architecture has a single-layer address space, and each device reserves a section of PCIE spa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38G06F13/42
Inventor 陈春明
Owner NEW H3C TECH CO LTD