Accelerator, information processing apparatus and information processing method
An information processing device and accelerator technology, which is applied in the direction of data processing power supply, etc., can solve the problems of CPU overload, without considering multiple computing components of the accelerator, etc.
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Embodiment 1
[0022] First, according to figure 1 , the configuration of the information processing device according to Embodiment 1 of the present invention will be described. figure 1 is a configuration diagram showing the configuration of the information processing device of this embodiment.
[0023] The information processing device 1 is configured to include a PC 2 having a PC design structure (architecture). PC2 can attach, ie connect to accelerator 3 . The PC 2 is an information processing device configured to include a CPU (Central Processing Unit) 11, an MCH (Memory Controller Hub) 12, an ICH (I / O Controller Hub) 13, a GPU (Graphics Processing Unit) 14, a main memory 15, as VRAM (VideoRAM) 16 for video memory. Therefore, the accelerator 3 is connected to the PC 2 having such a PC structure to constitute the information processing device 1 . In addition, in this embodiment, an example of a PC structure composed of CPU 11 , MCH 12 , ICH 13 , and GPU 14 was shown as the PC structu...
Embodiment 2
[0091] Next, Embodiment 2 of the present invention will be described. The AC for the information processing device of Embodiment 2 not only has a plurality of general-purpose processing elements (PE), but also has a plurality of hardware macros (hard macros). For the actions of the plurality of hardware macros, the allocation of processing is also determined, and the control is as follows: Optimal power consumption execution processing.
[0092] Figure 9 It is a block diagram showing the configuration of AC3A of the second embodiment. The same reference numerals are assigned to the same constituent elements as AC3 in Embodiment 1, and explanations thereof are omitted.
[0093] like Figure 9 As shown, AC3A has multiple (here, two) encoders 26A, 26B and multiple (here, two) decoders 26C, 26D as hardware macros, and is connected to CPE 21 via internal bus 25 . Hereinafter, when all of the encoders 26A, 26B, and decoders 26C, 26D are indicated, or when one of them is indicated...
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