TEG pattern and semiconductor device test method using same

Abstract

The invention relates to a TEG pattern and a method for testing a semiconductor device using the TEG pattern. The TEG pattern includes: a plurality of device isolation layer patterns having predetermined gaps between adjacent active regions; active region patterns in adjacent device isolation layer patterns; and metal contacts in the active region patterns pattern.

Description

technical field [0001] The present invention relates to a TEG pattern (Test Element Group Pattern) and a method of testing a semiconductor device using the TEG pattern. Background technique [0002] In order to confirm whether the processing results of each process in the semiconductor manufacturing process are acceptable or preferred, the thickness, resistance, density, contamination, critical dimension and electronic characteristics of the device or structure should be measured. During such measurements, wafers of semiconductor devices may be damaged. As such, one may not be able to monitor characteristics of the actual wafer in process (ie, during the fabrication process or between processing steps while the wafer is still in the semiconductor fabrication facility). [0003] In this case, a pattern called TEG (Test Element Group) is formed on a predetermined portion of the wafer or on a separate blank wafer, and processing is performed under the same conditions as those ...

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Problems solved by technology

[0008] However, according to the prior art, electronic devices capable of effectively monitoring the stack misalignment of Metal 1 Contacts (M1C) in this active region have not been systematically developed in the manufacture of semiconductor devices at 90nm or smaller technology nodes. Test modules and test modules that can accurately monitor the leakage characteristics of the PN junction diode region

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