Latency insensitive FIFO signaling protocol

Abstract

Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

Description

technical field [0001] The subject matter of the present invention relates to protocols for signaling and control, and to data transfer via first-in-first-out (FIFO) storage devices and devices implementing such signaling protocols. Background technique [0002] First-in-first-out (FIFO) memory devices are used in processor and communication applications that involve data transfer between different domains, typically where the domains can operate at different data rates. Although data rates differ or often vary between domains, signals between domains may be clocked relative to the same base clock frequency (ie, synchronous), or clocked relative to a different base clock frequency (ie, asynchronous). In synchronous applications, the buffering provided by the FIFO compensates for the difference in data rates of the two domains. In asynchronous applications, the buffering provided by the FIFO compensates for differences in both data rates and clock frequencies of the two dom...

AI Technical Summary

Problems solved by technology

[0003] However, most FIFO implementations are constrained by the limited size or depth of the memory or registers implementing the FIFO buffers

For example, if the sending domain sends more data when the FIFO storage is already full of data waiting to be delivered to the data sink in the receiving domain, the data will still be lost

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