Redundant clock signal commutation circuit and method

Abstract

The invention discloses a redundancy clock signal switching circuit and a method, clock signals with a plurality of lines in the circuit are respectively connected with an input end of a clock signal overlapping unit, the clock signals with a plurality of lines are output as the clock signal of a single plate or an unit plate after the overlapping processing by the clock signal overlapping unit; and each line of clock signal is carried out the on-off control by the corresponding switching control end. The usage of the switching circuit and the method which are proposed by the invention can not affect the continuity which is supplied to the single plate clock once the clock signals are turned off due to the faults or needs, thus ensuring no interruption of the business of the system.

Description

technical field [0001] The invention relates to the field of computer communication, more specifically to a switching circuit and a method for a single board to receive redundant clock signals in a computer communication hardware platform. Background technique [0002] There are many ways to realize the redundant processing technology of the system clock signal in the current communication hardware platform. According to the single board (or unit) that receives the system clock in the system, there are several input channels for the same clock signal. can be roughly divided into two categories: [0003] 1) For the same clock signal of the system, the single board (or unit) that needs to receive the system clock can only have one input at any time. In this case, the switching of redundant clock signals in system design is generally placed at the clock signal sending end. [0004] 2) For the same clock signal of the system, the single board (or unit) that needs to receive th...

AI Technical Summary

Problems solved by technology

The switching method in the prior art cannot overcome the impact on the system caused by the time difference of the switching action caused by the loss of the main clock signal CLK1A (assuming that the system selects CLK1A as the main clock signal) to the S1 switching control terminal. In general, the interruption of the system will directly cause the interruption of the system business

There is also a lack of a simple and effective circuit and method for switching redundant clock signals at the receiving end in the prior art

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