Technique for reducing crystal defects in strained transistors by tilted preamorphization

Abstract

By performing a tilted amorphization implantation (208, 308P, 308N) and a subsequent re-crystallization on the basis of a stressed overlying material (209, 211, 309, 311, 319S), a highly efficient strain-inducing mechanism is provided. The tilted amorphization implantation (208, 308P, 308N) may result in a significantly reduced defect rate during the re-crystallization process, thereby substantially reducing leakage currents in sophisticated transistor elements (200, 300N, 300P).

Description

technical field [0001] The present invention relates generally to the formation of integrated circuits and, more particularly, to forming channels with strained channel regions by using stress inducing sources such as embedded strain layers and the like. transistors to increase the charge carrier mobility in the channel region of the MOS transistor. Background technique [0002] Manufacturing integrated circuits requires forming a large number of circuit elements on a given chip area according to a specified circuit layout. Generally speaking, various process technologies are implemented at present, among them, for complex circuits, such as microprocessors, memory chips, and the like, CMOS technology is currently one of the most promising methods, because by operating Speed ​​and / or power consumption and / or cost efficiency appear to be excellent characteristics. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, ie, N-chan...

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Problems solved by technology

However, during operation of the device 100, a significant increase in leakage current is observed, believed to be caused by a crystalline defect 114, also known as a "zipper defect," and possibly representing a minority charge The source of carrier carrier lifetime reduction, which can significantly contribute to the increase in leakage current

[0015] Although the approach described above with reference to FIGS. 1a-1c may provide the potential for significant performance gains for both N-channel and P-channel transistors, the increased leakage current results in the formation of sophisticated transistor devices using this prior art technique. would be less attractive

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