Electric charge sharing mode LCD device, source drive device and electric charge sharing method
A liquid crystal display and charge sharing technology, applied in static indicators, instruments, nonlinear optics, etc., can solve the problems of high cost, power consumption and large area of the driver chip, and achieve the effect of reducing power consumption and simple control timing
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Embodiment 1
[0027] According to the liquid crystal display of the present invention, it includes a liquid crystal display, a grayscale generation circuit, a source driver, a gate driver and a logic control sequential circuit, and the structure of the liquid crystal display is as follows figure 1 As shown, a plurality of thin film transistors N1, a plurality of gate lines G1 and G2 insulated from each other and a plurality of data lines S1 and S2 are fabricated on the panel, and the gate, source and drain of each thin film transistor N1 are respectively connected to adjacent The gate line, data line and pixel electrode (not shown in the figure), the gate line is connected to the output terminal of the gate driver, and the data line is connected to the output terminal of the source driver. The gray scale generating circuit outputs the gray scale voltage to the source driver.
[0028] Such as figure 2 As shown, the source driver includes a sequentially connected source drive latch, a digit...
Embodiment 2
[0048] The difference between this embodiment and the first embodiment is that only the logic control sequence circuit is required to control the second switch circuit and the third switch circuit to have at least one coincidence that makes the second switch circuit and the third switch circuit conduct simultaneously. conduction period M, and the logic control sequence circuit controls the first switch circuit to be in an off state during at least one coincident conduction period, such as Figure 7 As shown, the first control sequence C1, the second control sequence C2 and the third control sequence C3 are periodic signals with the same cycle, the high level turns on the transistor, and there is a coincident conduction period M in each cycle , in the coincident conduction period M, the transmission gate T2 and the transmission gate T3 are simultaneously turned on, while the transmission gate T1 is turned off, and the conduction and disconnection of the thin film transistor have...
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