Chip and manufacturing method thereof
A chip and liner technology, applied in the field of chips and their manufacturing, can solve problems such as damage and impact on chip yield
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[0046] see Figure 2A , Figure 2A is a schematic diagram of a chip 1 according to a specific embodiment of the present invention. Such as Figure 2AAs shown, the chip 1 includes a plurality of first conductive pads 10 and a plurality of second conductive pads 12 approximately in the shape of water droplets. The first conductive linings 10 and the second conductive linings 12 are arranged alternately in a predetermined direction D, respectively. Each first conductive lining 10 includes a first portion P1 and a second portion P2 corresponding to the first portion P1 , and the length of the first portion P1 along the predetermined direction D is greater than the length of the second portion P2 along the predetermined direction D. Each second conductive lining 12 includes a third portion P3 and a fourth portion P4 relative to the third portion P3, and the length of the third portion P3 along the predetermined direction D is greater than that of the fourth portion P4 along the ...
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