Chip and manufacturing method thereof

A chip and liner technology, applied in the field of chips and their manufacturing, can solve problems such as damage and impact on chip yield

Inactive Publication Date: 2009-05-06
RAYDIUM SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] On the other hand, the corner area of ​​the chip is often damaged by the stress generated by the packaging process, which affects the chip yield

Method used

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  • Chip and manufacturing method thereof
  • Chip and manufacturing method thereof
  • Chip and manufacturing method thereof

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Experimental program
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Embodiment Construction

[0046] see Figure 2A , Figure 2A is a schematic diagram of a chip 1 according to a specific embodiment of the present invention. Such as Figure 2AAs shown, the chip 1 includes a plurality of first conductive pads 10 and a plurality of second conductive pads 12 approximately in the shape of water droplets. The first conductive linings 10 and the second conductive linings 12 are arranged alternately in a predetermined direction D, respectively. Each first conductive lining 10 includes a first portion P1 and a second portion P2 corresponding to the first portion P1 , and the length of the first portion P1 along the predetermined direction D is greater than the length of the second portion P2 along the predetermined direction D. Each second conductive lining 12 includes a third portion P3 and a fourth portion P4 relative to the third portion P3, and the length of the third portion P3 along the predetermined direction D is greater than that of the fourth portion P4 along the ...

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PUM

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Abstract

The invention discloses a chip and a manufacturing method thereof. The manufacturing method of the chip comprises the following steps: arranging a plurality of first conducting gaskets on the chip along one direction, wherein the first conducting gasket comprises a first part and a second part relative to the first part, and the length of the first part along the direction is larger than that of the second part along the direction; and arranging a plurality of second conducting gaskets arranged with the first conducting gaskets in a staggered manner on the chip, wherein each second conducting gasket comprises a third part and a fourth part relative to the third part, and the length of each third part along the direction is larger than that of the fourth part along the direction. The direction from the third part to the fourth part is opposite to the direction from the first part to the second part. The chip and the manufacturing method thereof can ensure that the conducting gaskets are densely arranged on the chip; and the design of the conducting gaskets at the corner can reduce the pressure damage of the chip generated during the encapsulation process.

Description

technical field [0001] The present invention relates to a chip and its manufacturing method, and in particular, the present invention relates to a chip with a denser arrangement of conductive pads and a conductive pad design that can reduce pressure damage at the corner of the chip and its manufacturing method. Background technique [0002] In recent years, due to the rapid development of semiconductor technology, the functions of chips have become more and more diverse. Correspondingly, the circuit design required for the function of the chip is becoming more and more complex, so that on a single chip, the number of conductive pads acting as contacts for providing electronic signals increases accordingly. When the number of conductive linings exceeds a certain level, it will directly affect the size of the chip and reduce the number of chips that can be cut out of a unit wafer. In this way, the cost of chip production increases accordingly. Furthermore, an oversized chip ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/485
CPCH01L24/05H01L24/06H01L2224/05552H01L2224/05554
Inventor 左克扬王威徐嘉宏周忠诚
Owner RAYDIUM SEMICON
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