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RS encoding apparatus and encoding method based on FPGA

An encoding device and encoding technology, which are applied in the field of digital encoding, can solve the problems that bit serial operations are difficult to meet design requirements, complex RS encoding algorithms, and many hardware resources, and achieve reduced overhead, low complexity, and simplified hardware circuits. Effect

Inactive Publication Date: 2011-06-29
SHANDONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The traditional RS coding algorithm is complicated, takes up a lot of hardware resources, and costs a lot
In RS coding, the core device used is the constant-coefficient Gale Huayu multiplier. Common implementation methods include Berlekamp and Massey-Omura bit-serial multipliers, Mastrovito bit-parallel multipliers, especially Berlekamp bit-serial multipliers The hardware structure is simpler when applied to the RS code, but when the data throughput rate is high, because the Berlekamp bit-serial multiplier involves two bases, the bit-serial operation is difficult to meet the design requirements

Method used

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  • RS encoding apparatus and encoding method based on FPGA
  • RS encoding apparatus and encoding method based on FPGA
  • RS encoding apparatus and encoding method based on FPGA

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Embodiment 1

[0057] A kind of RS coding device based on FPGA, comprises a pc machine 1, a development board 3, it is characterized in that the parallel port of pc machine 1 is connected with development board 3 by a JATG connection line 2, and device has FPGA on the development board 3 Chip 4.

[0058] The configured FPGA chip 4 includes a Galois field adder unit, a Galois field multiplier unit, a register and a selector.

Embodiment 2

[0060] A kind of method utilizing the RS encoding device of above-mentioned FPGA to encode, the steps are as follows:

[0061] (1) When the packet synchronization signal is detected, all registers D 0 D. 1 …D 15 Clear;

[0062] (2) For the first 188 bytes of each frame, K2 is on b, at the same time K1 is closed, and 188 input data are sequentially shifted out on the rising edge of the data clock, and each input data is connected with D at the same time 15 Register XOR is used as the multiplier of 16 multipliers. In order to improve the data throughput, we use pipeline technology to perform multiplication on the rising edge of the data, and XOR operation on the falling edge;

[0063] (3) After 188 bytes are passed, K2 hits a, while K1 is disconnected, and the feedback loop is set to zero, passing D in the next 16 clocks 15 The 16 check bytes are shifted out in order to complete the encoding of a packet, and when the packet synchronization signal of the next packet is detect...

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Abstract

A RS encoding device based on FPGA and an encoding method belong to the technical field of numerical coding. The encoding device comprises a pc machine and a development board, and is characterized in that a parallel port of the pc machine is connected with the development board by a JATG connecting line, and the development board is equipped with an FPGA chip which includes a Galois Field (GF) adder unit, a GF multiplier unit, a register and a selector. The RS encoding device and the encoding method can simplify a hardware circuit to reduce the spending of the system and save the cost, thus realizing the RS encoding device and the encoding method which have high speed and low complexity.

Description

1. Technical field [0001] The invention relates to an FPGA-based RS coding device and a coding method, belonging to the technical field of digital coding. 2. Background technology [0002] Reed-solomn (Reed-Solomon) code is a kind of strong error correction code, which belongs to a kind of BCH code, and is also a typical algebraic geometry code. It was constructed by Reed and Solomon in 1960 using MS polynomials, and it is a good class of linear error-correcting codes. RS coding has a strong application space and is widely used in communication systems, digital television and computer storage systems. [0003] The traditional RS coding algorithm is complicated, takes up many hardware resources, and costs high. In RS coding, the core device used is the constant-coefficient Gale Huayu multiplier. Common implementation methods include Berlekamp and Massey-Omura bit-serial multipliers, Mastrovito bit-parallel multipliers, especially Berlekamp bit-serial multipliers The hardwa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/15
Inventor 刘志军孔德超于帅韩庆喜
Owner SHANDONG UNIV