Exhaustive diagnosis of bridging defects in an integrated circuit

一种集成电路、缺陷的技术，应用在电子电路测试、边际电路测试、测量电等方向，能够解决没有提供令人满意解决方案等问题

Inactive Publication Date: 2009-06-17
GLOBALFOUNDRIES INC
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

The current state of the art does not provide a satisfactory solution to this need

Method used

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  • Exhaustive diagnosis of bridging defects in an integrated circuit
  • Exhaustive diagnosis of bridging defects in an integrated circuit
  • Exhaustive diagnosis of bridging defects in an integrated circuit

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Embodiment Construction

[0027] The following detailed description of the embodiments refers to the accompanying drawings showing specific embodiments of the present invention. Other embodiments having different structures and operations do not depart from the scope of the present invention.

[0028] The best way to implement the invention

[0029] Reference figure 1 , A schematic diagram of an explanatory bridge defect diagnosis system (diagnostic system) 10 is shown. According to one embodiment, the diagnostic system 10 includes: an integrated circuit (IC) 20 including a plurality of nodes that should be aware of; a test vector source 30 including a test vector generator 32 and a tester 34; DDQ The measurer 40; the logic state detector 50; and the bridge defect diagnostic device 60. The integrated circuit (IC) 20 may be coupled between the positive power supply (VDD) 22 and the ground 24. In operation, the test vector generator 32 generates a test vector, and the tester 34 inputs the generated test vec...

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Abstract

A method, system and computer program product for diagnosing a bridging defect in an integrated circuit including multiple nodes (20) are disclosed. Quiescent power supply current (IDDQ) of the integrated circuit (IC) is measured (40) under multiple test vectors (30). Logic states of the nodes on the IC are also obtained (20) under the multiple test vectors (30). The nodes are partitioned (S3) into sets based on their logic states under low-current test vectors. Large sets are further divided into subsets ('state-count subsets') (S 5-1) based on the logic states of nodes under high-current test vectors. For large sets, explicit evaluation under the IDDQ bridge fault model is performed only on pairs of nodes belonging to subsets having complementary state counts (S5-2, S5-3), to save system resources in computation. Exhaustive diagnosis considering all pairs of nodes on the IC is thus feasibly achieved due to the saving of system resources.

Description

Technical field [0001] The present invention generally relates to diagnosing faults in integrated circuits, and more particularly to diagnosing bridging defects in integrated circuits. Background technique [0002] The logic and electrical behavior of bridging defects, which are unintentional electrical connections or "short circuits" between nodes in integrated circuit (IC) design, has long been the subject of research in the testing community. Bridging defects are the main cause of loss in IC manufacturing yield, so reducing their number has significant financial benefits for IC manufacturers. Bridge defects, especially high-resistance bridges, can also evade detection in manufacturing testing. An IC with an undetected bridge can thus be erroneously shipped to the customer, where it can fail immediately or after an extended period of use. [0003] The ability to anticipate and adapt to the changing behavior of bridging defects is more important to success in fault diagnosis whe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG01R31/3008G01R31/2853
Inventor D·C·希伯林
Owner GLOBALFOUNDRIES INC
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