7 results about "Bridging fault" patented technology

The embodiment of the invention provides a semiconductor device, a design method thereof and electronic equipment, relates to the technical field of semiconductors, and aims to solve the problems of relatively low yield and reliability of a chip and the like. The semiconductor device comprises a first bare chip, a second bare chip and a plurality of interconnection ports, the first bare chip comprises a plurality of shift transmitting circuits, the second bare chip comprises a plurality of shift receiving circuits, and the ith signal output end of each shift transmitting circuit is connected with the ith signal input end of the corresponding shift receiving circuit through the ith interconnection port to form a shift transmission circuit; any two adjacent interconnection ports of the semiconductor device are connected in different shift transmission circuits, and when the two adjacent interconnection ports have a bridging fault, the different shift transmission circuits can perform shift repair on the interconnection ports.

This invention discloses a switchless redundant fault-tolerant memristor cross array circuit for resolving bridging faults, comprising a main array, two redundant word lines, two redundant bit lines, and a controller. The main array consists of N word lines, M bit lines, and cross-point memristor cells. The redundant word lines cross with all bit lines, and the redundant bit lines cross with all word lines. The controller is directly connected to all word lines, redundant word lines, bit lines, and redundant bit lines. This circuit does not contain any physical switches for fault isolation, has a simple structure, low hardware overhead, and is easy to integrate.

The application discloses a kind of TSV bonding post-detection circuits based on positive feedback, comprising: transmission gate switch array, cross-coupled pair tube, reset module, test capacitor, eliminate parasitic module, resistance array, receiving buffer.The application utilizes the positive feedback characteristics of cross-coupled pair tube, accelerates comparison process and improves detection sensitivity, the time required for detection process is greatly reduced, and the detection circuit structure is simple;Utilize resistance array to compare the cavity resistance R TSV And leakage resistance R leakage Of the TSV to be tested, realize effective detection of cavity fault and leakage fault;Through the switching of transmission gate switch array, the cross-coupled pair tube can be equivalent to a current source, and the test capacitor and receiving buffer are used to realize effective detection of bridging fault and open-circuit fault.

The invention discloses a bridging fault online monitoring method for memristor matrix vector multiplication. According to the core scheme, a parity check test pair and a single word line activation test sequence are applied to array word lines; measuring bit line output current, and calculating a deviation vector between the bit line output current and the fault-free base line; and positioning the fault by identifying the characteristic mode of the deviation vector. And three types of bridging faults of bit line-bit line, word line-word line and word line-bit line can be accurately distinguished and positioned. The method does not need external equipment, can be integrated in a chip for periodic self-inspection, is low in hardware overhead, and provides a high-reliability fault monitoring solution for a computing system in a memristor memory.

The application belongs to the technical field of motor fault detection, and is especially a motor controller power switch device fault detection method and circuit, wherein the method comprises the following modes: static detection, after MCU power-on initialization, firstly execute the normal fault detection program, and simultaneously wait for C1 charging, after C1 charging is completed, the power switch device detection program starts to run, firstly carries out static self-checking, three-phase output voltage circuit sampling circuit will respectively send three-phase voltage output values after voltage division by R5 and R6 into the ADC of MCU for sampling, at this time, the MCU judges the voltage values of each phase, the three-phase output voltage all satisfies "less than VBUS-1V and greater than 0.1V", and is preliminarily judged to be normal, then the next dynamic detection is carried out, if not satisfied, continue to judge "any phase voltage is greater than VBUS-1V", the application can detect the fault of the power inverter unit before each start-up operation, and can accurately identify whether the controller power unit belongs to upper bridge fault or lower bridge fault, and in addition, whether the motor is open-phase can also be detected.

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device and a design method therefor, and an electronic device, which are used for alleviating problems such as the relatively low yield and reliability of chips. The semiconductor device comprises: a first die, a second die and a plurality of interconnection ports, wherein the first die comprises a plurality of shift transmission circuits, the second die comprises a plurality of shift reception circuits, and an ith signal output end of each shift transmission circuit is connected to an ith signal input end of each shift reception circuit by means of an ith interconnection port, so as to form a shift transfer circuit; and any two adjacent interconnection ports of the semiconductor device are connected to different shift transfer circuits, and when a bridging fault occurs in any two adjacent interconnection ports, shift repair can be respectively performed on the interconnection ports by means of different shift transfer circuits.

The invention discloses a built-in self-test method for detecting and positioning an ILV hard fault in an M3D circuit, which is used for detecting an interlayer interconnection ILV of a monolithic three-dimensional integrated circuit and comprises the following steps of: 1) initializing a test and setting a test mode; 2) applying full '0' excitation, and detecting a fixed fault of the through hole ILV; 3) applying full '1' excitation, and further detecting a fixed fault of the through hole ILV; 4) storing a fixed fault detection result into a scan chain; 5) applying bit-by-bit '1' excitation, detecting a bridging fault of the ILV, and moving a bridging fault detection result into the scanning chain while moving a fixed fault detection result out of the scanning chain; according to the method, special requirements for arrangement of the ILV are avoided, fixed faults and bridging faults in the ILV can be effectively detected and positioned, the time for occupying the ILV in a test mode is short through the time sequence design of parallel detection and shifting operation, and therefore the test efficiency can be improved.