32 results about "Bridging fault" patented technology

An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps include creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, receiving the physical data associated with nets of the circuit, applying adjacency criteria to the physical data, generating a pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria, performing in-line inspection to obtain second localized probable defect data and correlating second localized portable defect data with the pruned diagnostic list.

The invention discloses a method for monitoring a bridge fault on the basis of a video image and belongs to the technical field of a bridge monitoring method. The method is characterized by comprising the following steps of: (1) obtaining a video data of a preset position on a bridge; (2) comparing the video data; (3) obtaining a bridge fault condition; and (4) evaluating the use condition of the bridge and early warning. The invention aims to provide a high-detection-efficiency, high-accuracy and low-cost method for monitoring the bridge fault on the basis of the video image. The method is used for monitoring the bridge fault in real time.

The test pattern generating apparatus comprises a module configured to generate short information indicative of a relationship between a logical value of an input signal of a cell and a voltage of an electrically shorted portion assumed at an output terminal of the cell; a module configured to calculate a logical threshold value of the input terminal of the cell so as to generate logical threshold value information; a module configured to extract a bridge fault information from layout information of an LSI; a module configured to generate a bridge fault list including a bridge fault type based on the bridge fault information, the short information, and the logical threshold value information; and a module configured to generate a test pattern which detects bridge faults in an adjacent signal wire pair and a bridge fault type.

A method and mechanism for detecting interconnect and bridge defects. Contact points in a chip are assigned placement designation such that no two adjacent points have the same designation. A transmitter, receiver, and optional transmitter/receiver test are then run. During the transmitter test, transmitters with a given designation drive a particular test pattern while other transmitters drive a different test pattern. Receivers compare received test patterns against expected patterns. During a receiver test, transmitters drive a test pattern corresponding to the placement designation of the receivers to which they are coupled. During a particular receiver test, transmitters coupled to receivers of a given designation drive a particular stream, while other transmitters drive a different stream. Receivers then compare received streams against an expected stream. Finally, the placement designation of a transmitter or receiver of an adjacent transmitter/receiver pair may be temporarily assigned an alternate designation. A transmitter or receiver test is then run and receivers check received test patterns against expected patterns.

A boundary scan compatible device includes functionality for use in diagnosing the presence of bridging faults within associated circuitry. In at least one embodiment, a boundary scan compatible device includes functionality for detecting an intermediate signal level on an electrical node of the device (e.g., a pin on a circuit package, etc.) that is indicative of a bridging fault. Various structures are provided that are capable of detecting an intermediate signal level.

A method, system and computer program product for diagnosing a bridging defect in an integrated circuit including multiple nodes are disclosed. Quiescent power supply current (I_DDQ) of the integrated circuit (IC) is measured under multiple test vectors. Logic states of the nodes on the IC are also obtained under the multiple test vectors. The nodes are partitioned into sets based on their logic states under low-current test vectors. Large sets are further divided into subsets (“state-count subsets”) based on the logic states of nodes under high-current test vectors. For large sets, explicit evaluation under the I_DDQ bridge fault model is performed only on pairs of nodes belonging to subsets having complementary state counts, to save system resources in computation. Exhaustive diagnosis considering all pairs of nodes on the IC is thus feasibly achieved due to the saving of system resources.

The invention relates to a method for testing Virtex architecture-based field programmable gate array (FPGA) single-long line slant switches. The Virtex architecture-based FPGA single-long line slant switches are tested only by four-time configuration. The method has the advantages that: the single-long line slant switches of a FPGA circuit are tested in a shifting register chain mode, so that bridging failure between signals of any two single-long lines in the 24 single-long lines which are used as one group can be tested; the single-long line slant switches of all configurable logic blocks can be tested only by using four sections of configuration codes; a test process is simplified by the initial configuration of Blockram, so the method is convenient to operate by users; the failure positioning is accurate and is subjected to the four-time configuration, and can be corrected to the single-long line slant switches of the four CLBs under the condition that the position deviation of the CLBs in the latter two-time configuration is 4; and a basic structure which takes a row as a snakelike channel is changed into a basic structure which takes a line as the snakelike channel under the condition that the requirement of the failure positioning is extreme accurate, so the failure positioning can be corrected to the specific single-long line slant switches which are determined uniquely and correspond to the CLBs by eight-time configuration.

The invention relates to a testing method for FPGA (field programmable gate array) single long wires and directly connected switches based on a Virtex structure, which comprises four configuration steps. The invention has the advantages that: the shift register chain mode is adopted to test 24 single long wires of an FPGA circuit, and bridging faults between signals of any two of the 24 wires in one group can be tested; the single long wires and directly connected switches of all CLBs (configurable logic blocks) can be tested only with four configuration codes; the testing process is simplified and the user operation is facilitated through initial configuration of the Blockram; the faults can be accurately positioned, four configuration steps are included, and when the deviation of the CLB positions in the last two configuration step is 4, the faults can be accurately positioned for the directly connected switches or single long wires of four CLBs; and when the fault positioning requirements are extremely accurate, the deviation of the CLB positions can be defined as 1, two configuration steps in total are adopted, and the fault can be accurately positioned for the directly connected switch or single long wire corresponding to one specific and unique CLB.

The method for creating a test pattern and calculating a fault coverage or the like of the present invention is characterized by creating bridging fault voltage information indicating a voltage of a bridging assumed on the wire derived from an output terminal of a cell, calculating a logical threshold of an input terminal of the cell, extracting bridging fault information on an adjacent wire pair, calculating a detection limit resistance value using the logical threshold, adding the detection limit resistance value to bridging fault voltage information, creating extended bridging fault voltage information, creating a bridging fault list including a bridging fault type based on the extended bridging fault voltage information, creating a test pattern based on the bridging fault list, judging whether or not a bridging fault can be detected through this test pattern, creating fault detection information and calculating a weighted fault coverage based on the fault detection information and bridging fault generation information.

The invention discloses a bridging fault simulation device of an optical router and a control method. An analog multiplexer A is connected with two switchable first connecting branch components; the first connecting branch component is connected to the input of the either-or multiplexer 01, and the output of the either-or multiplexer 01 is output from the output port Q11 and the output port Q32 through an OR gate connected with the first connecting branch component; an analog multiplexer B is connected with the two switchable second connecting branch components; the second connecting branch component is connected to the input of the either-or multiplexer 02; and the output is output from the output port Q21 and the output port Q31 through an OR gate connected with the second connection branch component, so a single bridging fault of the MRR caused by heat sensitivity can be effectively simulated, and an important role is played in improving the reliability of the network-on-chip.

The method includes steps: (1) when learning that fault of the fault point in RPR bridge ring is recovered to normal, the method sets up maximal transmission unit value of the fault recovery node (FRN) to a prearranged value, and sends notification message in use for informing the fault point that the fault is recovered to transannular bridge device (TBD) in RPR bridge ring; (2) each RPR TBD in RPR bridge ring receives the notification message sent from FRN, as well as tests operating mode of each RPR TBD, and makes only one RPR TBD keep in main use state. Through cooperation between FRN and TBD, the invention ensures that transannular operation is forwarded correctly so as to solve loop issue occurs possibly after the fault point is recovered.

A bridge fault removal apparatus includes a bridge fault extraction unit configured to extract a bridge fault from layout information of a semiconductor integrated circuit, a test pattern generator configured to generate the test pattern aiming at the bridge fault extracted by the bridge fault extraction unit, a logical value information calculator configured to calculate logical value information of all the signals in the semiconductor integrated circuit by applying the test pattern generated by the test pattern generator to logical connection information of the semiconductor integrated circuit, and a bridge fault remover configured to select an exchange signal candidate for an undetected bridge fault signal corresponding to the test pattern based on the logical value information calculated by the logical value information calculator.

The invention provides a bridge fault detection device. The bridge fault detection device comprises a vibration sensor group, a first-stage operational amplifier, a filter, a second-stage operational amplifier and a processor which are sequentially connected, wherein the vibration sensor group is used for converting acquired bridge vibration information into a current signal and transmitting the current signal to the first-stage operational amplifier; the first-stage operational amplifier is used for amplifying the current signal for the first time, generating a first voltage signal and transmitting the first voltage signal to the filter; the filter is used for carrying out filtering treatment on the first voltage signal and transmitting the filtered first voltage signal to the second-stage operational amplifier; the second-stage operational amplifier is used for amplifying the filtered first voltage signal for the second time, generating a second voltage signal and transmitting the second voltage signal to the processor; and the processor is used for carrying out preset analysis on the received second voltage signal for obtaining analysis results. Therefore, a manual detection manner is replaced, all the faults of a bridge can be more comprehensively detected, detection accuracy can be improved, and potential safety hazard of personnel during detection can be avoided.

The invention discloses a method for judging the IDDQ test result by using the current difference value delta IDDQ (MAX(IDDQ_1, IDDQ_N)-MIN(IDDQ_1, IDDQ_N)) and using the result for improving the IDDQfault and the bridging fault test coverage rate. By using the method, the existing method of judging the IDDQ only by using two test points can be improved, and the test points are widened to any onetest point. Through the additional addition of the test points, the test coverage rate of the IDDQ test can be improved. Meanwhile, a current difference value is used as the basis for judging the IDDQ test; the defect of heavy background current under the deep sub-micron process conditions through the single judging of the current intensity during the IDDQ test can be reduced. The stable mass production during the chip mass production under the background of process deviation existence can be further ensured.

According to the invention, the DRAM to be tested is subjected to two rounds of testing, all the storage units written with the preset testing data are subjected to row alternate access, the comparison result is obtained in the row alternate access process, and the final testing result is obtained through the comparison result of the two rounds of testing; the invention can cover a previous test blind area and detect chip defects which are difficult to find in the prior art, so that multiple storage unit faults such as bridging faults and coupling faults are stimulated, the fault coverage rateis improved, the reliability of a test result is enhanced, and the benign of a product is improved.

The invention discloses an optical router bridging fault positioning method based on a single fault model, and the method comprises the following steps: initializing the specific attributes of each input port and each output port of an optical router, classifying micro-ring resonators in the optical router, and dividing the micro-ring resonators into inlet resonators and outlet resonators; grouping the inlet resonators according to the connected input ports, and inputting test signals corresponding to the inlet resonators at the input ports according to the inlet resonators; after a to-be-tested signal is input, acquiring a first signal detected by each output port of the optical router, comparing the first signal with a standard output signal of each output port of the optical router in a fault-free state, and if the first signal does not conform to the standard output signal of each output port, determining the micro-ring resonator with the bridging fault according to the difference of the output signals.