32 results about "Bridging fault" patented technology

An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps include creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, receiving the physical data associated with nets of the circuit, applying adjacency criteria to the physical data, generating a pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria, performing in-line inspection to obtain second localized probable defect data and correlating second localized portable defect data with the pruned diagnostic list.

A method, system and computer program product for diagnosing a bridging defect in an integrated circuit including multiple nodes are disclosed. Quiescent power supply current (IDDQ) of the integrated circuit (IC) is measured under multiple test vectors. Logic states of the nodes on the IC are also obtained under the multiple test vectors. The nodes are partitioned into sets based on their logic states under low-current test vectors. Large sets are further divided into subsets (“state-count subsets”) based on the logic states of nodes under high-current test vectors. For large sets, explicit evaluation under the IDDQ bridge fault model is performed only on pairs of nodes belonging to subsets having complementary state counts, to save system resources in computation. Exhaustive diagnosis considering all pairs of nodes on the IC is thus feasibly achieved due to the saving of system resources.

A method, system and computer program product for diagnosing a bridging defect in an integrated circuit including multiple nodes (20) are disclosed. Quiescent power supply current (IDDQ) of the integrated circuit (IC) is measured (40) under multiple test vectors (30). Logic states of the nodes on the IC are also obtained (20) under the multiple test vectors (30). The nodes are partitioned (S3) into sets based on their logic states under low-current test vectors. Large sets are further divided into subsets ('state-count subsets') (S 5-1) based on the logic states of nodes under high-current test vectors. For large sets, explicit evaluation under the IDDQ bridge fault model is performed only on pairs of nodes belonging to subsets having complementary state counts (S5-2, S5-3), to save system resources in computation. Exhaustive diagnosis considering all pairs of nodes on the IC is thus feasibly achieved due to the saving of system resources.

The invention provides a single photon detection method and system for faults of an integrated circuit. According to the detection method, a set test vector is applied to a tested circuit, so that signal transition at the faults occurs, so that weak light is generated; and the weak light for the faults is detected by adopting a single photon detector. The detection system comprises a tested integrated circuit, an photon counting circuit module, a signal generator and a microcomputer, wherein the microcomputer is used for controlling the work of the whole system; and the microcomputer is also used for receiving detection data transmitted by the photon counting circuit module and comparing and analyzing the detection data with data in a database so as to realize detection and positioning of the faults in the circuit. According to the single photon detection method and system provided by the invention, various faults such as fixed faults, bridging faults, signal integrity faults and the like in the integrated circuit can be directly detected and positioned, and thereby the quality and the reliability of circuit chip products are improved.

The method includes steps: (1) when learning that fault of the fault point in RPR bridge ring is recovered to normal, the method sets up maximal transmission unit value of the fault recovery node (FRN) to a prearranged value, and sends notification message in use for informing the fault point that the fault is recovered to transannular bridge device (TBD) in RPR bridge ring; (2) each RPR TBD in RPR bridge ring receives the notification message sent from FRN, as well as tests operating mode of each RPR TBD, and makes only one RPR TBD keep in main use state. Through cooperation between FRN and TBD, the invention ensures that transannular operation is forwarded correctly so as to solve loop issue occurs possibly after the fault point is recovered.

The invention relates to a method for testing Virtex architecture-based field programmable gate array (FPGA) single-long line slant switches. The Virtex architecture-based FPGA single-long line slant switches are tested only by four-time configuration. The method has the advantages that: the single-long line slant switches of a FPGA circuit are tested in a shifting register chain mode, so that bridging failure between signals of any two single-long lines in the 24 single-long lines which are used as one group can be tested; the single-long line slant switches of all configurable logic blocks can be tested only by using four sections of configuration codes; a test process is simplified by the initial configuration of Blockram, so the method is convenient to operate by users; the failure positioning is accurate and is subjected to the four-time configuration, and can be corrected to the single-long line slant switches of the four CLBs under the condition that the position deviation of the CLBs in the latter two-time configuration is 4; and a basic structure which takes a row as a snakelike channel is changed into a basic structure which takes a line as the snakelike channel under the condition that the requirement of the failure positioning is extreme accurate, so the failure positioning can be corrected to the specific single-long line slant switches which are determined uniquely and correspond to the CLBs by eight-time configuration.