3 results about "Bridging fault" patented technology

This invention discloses a switchless redundant fault-tolerant memristor cross array circuit for resolving bridging faults, comprising a main array, two redundant word lines, two redundant bit lines, and a controller. The main array consists of N word lines, M bit lines, and cross-point memristor cells. The redundant word lines cross with all bit lines, and the redundant bit lines cross with all word lines. The controller is directly connected to all word lines, redundant word lines, bit lines, and redundant bit lines. This circuit does not contain any physical switches for fault isolation, has a simple structure, low hardware overhead, and is easy to integrate.

The invention discloses a bridging fault online monitoring method for memristor matrix vector multiplication. According to the core scheme, a parity check test pair and a single word line activation test sequence are applied to array word lines; measuring bit line output current, and calculating a deviation vector between the bit line output current and the fault-free base line; and positioning the fault by identifying the characteristic mode of the deviation vector. And three types of bridging faults of bit line-bit line, word line-word line and word line-bit line can be accurately distinguished and positioned. The method does not need external equipment, can be integrated in a chip for periodic self-inspection, is low in hardware overhead, and provides a high-reliability fault monitoring solution for a computing system in a memristor memory.

The invention discloses a built-in self-test method for detecting and positioning an ILV hard fault in an M3D circuit, which is used for detecting an interlayer interconnection ILV of a monolithic three-dimensional integrated circuit and comprises the following steps of: 1) initializing a test and setting a test mode; 2) applying full '0' excitation, and detecting a fixed fault of the through hole ILV; 3) applying full '1' excitation, and further detecting a fixed fault of the through hole ILV; 4) storing a fixed fault detection result into a scan chain; 5) applying bit-by-bit '1' excitation, detecting a bridging fault of the ILV, and moving a bridging fault detection result into the scanning chain while moving a fixed fault detection result out of the scanning chain; according to the method, special requirements for arrangement of the ILV are avoided, fixed faults and bridging faults in the ILV can be effectively detected and positioned, the time for occupying the ILV in a test mode is short through the time sequence design of parallel detection and shifting operation, and therefore the test efficiency can be improved.