Testing method for FPGA (field programmable gate array) single long wire and directly connected switch

Abstract

The invention relates to a testing method for FPGA (field programmable gate array) single long wires and directly connected switches based on a Virtex structure, which comprises four configuration steps. The invention has the advantages that: the shift register chain mode is adopted to test 24 single long wires of an FPGA circuit, and bridging faults between signals of any two of the 24 wires in one group can be tested; the single long wires and directly connected switches of all CLBs (configurable logic blocks) can be tested only with four configuration codes; the testing process is simplified and the user operation is facilitated through initial configuration of the Blockram; the faults can be accurately positioned, four configuration steps are included, and when the deviation of the CLB positions in the last two configuration step is 4, the faults can be accurately positioned for the directly connected switches or single long wires of four CLBs; and when the fault positioning requirements are extremely accurate, the deviation of the CLB positions can be defined as 1, two configuration steps in total are adopted, and the fault can be accurately positioned for the directly connected switch or single long wire corresponding to one specific and unique CLB.

Description

technical field [0001] The invention relates to an FPGA testing method based on a Virtex framework, in particular to a testing method for an FPGA single long line and its direct connection switch. Background technique [0002] The FPGA based on the Virtex architecture is a reprogrammable VLSI chip with a large number of wiring resources and a wide variety. Therefore, in the actual application of FPGA, the probability of faults occurring in interconnect resources is far greater than that occurring in other logic functions. [0003] At present, the well-known FPGA wiring switch testing technologies at home and abroad generally focus on small-scale wiring switches such as 3x3 and 4x4; and currently commercial FPGAs mostly use 24x24 wiring switches. In addition, due to the testing of FPGA products, the number of configuration codes is The key parameters that affect the test cycle, so how to use as few configuration codes as possible to complete the single-line wiring and switc...

AI Technical Summary

Problems solved by technology

[0004] Although there are so-called four-time and six-time configuration methods at home and abroad to complete the FPGA interconnect resource test, on the one hand, the above methods are based on a simple interconnect resource model; on the other hand, because no trigger signal is introduced in the test process, resulting The interconnection levels of wiring resources are too long, which is not conducive to fault location; and there is no clear and available detection method for the bridging fault model that may occur between wiring paths

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