Method for judging IDDQ test by using current difference value

A technology of current difference and current value, applied in the field of screening and testing of integrated circuit chips, can solve the problems of poor IDDQ test ability and deviation of processing technology.

Inactive Publication Date: 2018-11-09
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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Problems solved by technology

However, with the progress of the process size, the static power consumption of the chip has been increasing. The current during the pure IDDQ test is getting larger and larger with the progress of the process, but the current caused by the fault changes very little. In the mass production stage, the pro

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  • Method for judging IDDQ test by using current difference value

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Embodiment Construction

[0014] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0015] The test of IDDQ can be summarized as figure 1 The flow chart shown.

[0016] First configure the digital part of the chip to meet the first test pattern. Then test the power supply current of the chip, mark it as IDDQ_1, and judge whether the test result is within the SPEC range. In the test, the upper limit and lower limit of the test will be given according to each test item in the test specification, that is, to judge whether it is within the scope of the test SPEC.

[0017] It is recommended here that the average value of the entire wafer test for the FF biased wafer + 3 times Σ be used as the upper limit of the test. The average value -3 times Σ of the whole piece of the SS pull-off wafer is used as the lower limit of the test. The SPEC obtained in this way can ensure the stability of mass production. At the same time, record...

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Abstract

The invention discloses a method for judging the IDDQ test result by using the current difference value delta IDDQ (MAX(IDDQ_1, IDDQ_N)-MIN(IDDQ_1, IDDQ_N)) and using the result for improving the IDDQfault and the bridging fault test coverage rate. By using the method, the existing method of judging the IDDQ only by using two test points can be improved, and the test points are widened to any onetest point. Through the additional addition of the test points, the test coverage rate of the IDDQ test can be improved. Meanwhile, a current difference value is used as the basis for judging the IDDQ test; the defect of heavy background current under the deep sub-micron process conditions through the single judging of the current intensity during the IDDQ test can be reduced. The stable mass production during the chip mass production under the background of process deviation existence can be further ensured.

Description

technical field [0001] The invention belongs to the field of screening and testing of integrated circuit chips. By judging the leakage changes of the digital part of the chip in different states, the IDDQ fault and bridging fault of the chip are detected, thereby improving the screening test coverage. Background technique [0002] As the market's demand for the quality of semiconductor products increases, the industry needs to improve the test coverage in the screening test field. Especially for the high-reliability market (vehicle grade products), standards (such as AECQ100) clearly hope to introduce IDDQ testing. However, with the progress of the process size, the static power consumption of the chip has been increasing. The current during the pure IDDQ test is getting larger and larger with the progress of the process, but the current caused by the fault changes very little. In the mass production stage, the processing technology There will be deviations, and the curren...

Claims

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2853
Inventor 赵来钖
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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