Method for testing field programmable gate array (FPGA) single-long line slant switches

Abstract

The invention relates to a method for testing Virtex architecture-based field programmable gate array (FPGA) single-long line slant switches. The Virtex architecture-based FPGA single-long line slant switches are tested only by four-time configuration. The method has the advantages that: the single-long line slant switches of a FPGA circuit are tested in a shifting register chain mode, so that bridging failure between signals of any two single-long lines in the 24 single-long lines which are used as one group can be tested; the single-long line slant switches of all configurable logic blocks can be tested only by using four sections of configuration codes; a test process is simplified by the initial configuration of Blockram, so the method is convenient to operate by users; the failure positioning is accurate and is subjected to the four-time configuration, and can be corrected to the single-long line slant switches of the four CLBs under the condition that the position deviation of the CLBs in the latter two-time configuration is 4; and a basic structure which takes a row as a snakelike channel is changed into a basic structure which takes a line as the snakelike channel under the condition that the requirement of the failure positioning is extreme accurate, so the failure positioning can be corrected to the specific single-long line slant switches which are determined uniquely and correspond to the CLBs by eight-time configuration.

Description

technical field [0001] The invention relates to an FPGA testing method based on a Virtex framework, in particular to a testing method based on a Virtex framework FPGA single-line oblique switch. Background technique [0002] The user programmability, low development cost and short development cycle of field programmable gate array FPGA make it an important technology for realizing modern circuits and systems. In an FPGA chip, the wiring resources account for more than 60% of the chip area, and as the device scale increases, the interconnection resources become more and more complex, and the possibility of failure is very high, so the interconnection resource test is very important. [0003] At present, the well-known FPGA wiring switch testing technology at home and abroad does not focus on small-scale wiring switches such as 3×3 and 4×4, but Virtex series / SpartanII series FPGAs use 24×24 single-line wiring switches, with six long-line, Long lines, three-state control / data ...

AI Technical Summary

Problems solved by technology

[0005] Although there are so-called four-time and six-time configuration methods at home and abroad to complete the FPGA interconnect resource test, on the one hand, the above methods are based on a simple interconnect resource model; on the other hand, because no trigger signal is introduced in the test process, resulting The number of interconnection stages of wiring resources is too long, which is not conducive to fault location; and there is no clear and available detection method for the bridging fault model that may occur between wiring paths

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