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Optical router bridging fault positioning method based on single fault model

A technology of bridging faults and positioning methods, applied in the direction of selection devices, electrical components, selection devices, etc. of multiplexing systems, can solve problems such as drift, loss, MRR bridging faults, etc. good versatility

Pending Publication Date: 2021-07-13
GUILIN UNIV OF ELECTRONIC TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] MRR (Micro-Ring Resonators), the core device of the on-chip optical network, is very sensitive to temperature fluctuations. Temperature changes will cause the inherent resonance wavelength of the MRR to drift, resulting in bridging failures in the MRR.
In addition, the complex manufacturing process of MRR will also cause the resonant wavelength of MRR to drift to a certain extent, which will also cause bridge failure of the device, and eventually lead to misinformation or even loss of information, thereby reducing the performance and reliability of ONOC.

Method used

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  • Optical router bridging fault positioning method based on single fault model
  • Optical router bridging fault positioning method based on single fault model
  • Optical router bridging fault positioning method based on single fault model

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Embodiment Construction

[0024] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0025] In describing the present invention, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", The orientation or positional relationship indicated by "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than Nothing indicating or implying that a referenced device or element...

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Abstract

The invention discloses an optical router bridging fault positioning method based on a single fault model, and the method comprises the following steps: initializing the specific attributes of each input port and each output port of an optical router, classifying micro-ring resonators in the optical router, and dividing the micro-ring resonators into inlet resonators and outlet resonators; grouping the inlet resonators according to the connected input ports, and inputting test signals corresponding to the inlet resonators at the input ports according to the inlet resonators; after a to-be-tested signal is input, acquiring a first signal detected by each output port of the optical router, comparing the first signal with a standard output signal of each output port of the optical router in a fault-free state, and if the first signal does not conform to the standard output signal of each output port, determining the micro-ring resonator with the bridging fault according to the difference of the output signals.

Description

technical field [0001] The invention relates to the technical field of optical router bridging fault detection, in particular to a method for locating optical router bridging faults based on a single fault model. Background technique [0002] With the development of integrated circuits, blindly improving the performance of single-core processors can no longer increase the computing speed of the system, and even bring additional losses to the circuit. Therefore, it is inevitable for processors to develop from single-core chips to multi-core chips. Multi-core processors can improve the computing performance of chips without changing the original basic design. Network on chip is a chip design scheme proposed under the background of multi-core chip development. However, due to the increasing number of processor cores, the network-on-chip based on electrical interconnection further reduces the distance between cores due to its limited space, which will bring energy consumption a...

Claims

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Application Information

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IPC IPC(8): H04Q11/00
CPCH04Q11/0005H04Q11/0062H04Q2011/0083
Inventor 朱爱军古展其胡聪牛军浩万春霆唐源许川佩
Owner GUILIN UNIV OF ELECTRONIC TECH
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