Layout method capable of avoiding position-placed superimpose of throughhole and element words identification
A technology of character identification and layout method, which is applied in the direction of electrical connection formation of electrical components and printed components, electrical digital data processing, etc. Efficiency, avoid the appearance of joint effects, avoid overlapping effects
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[0015] The present invention will be described in detail below in conjunction with the accompanying drawings.
[0016] see figure 2 , which is a layout method according to an embodiment of the present invention to avoid overlapping placement positions of via holes and component text marks.
[0017] After starting the layout (as shown in step 202 ), it is first determined whether to place vias (as shown in step 204 ). When judging that the via hole is to be placed, a via hole placement operation (as shown in step 208) is performed, and then it is judged whether the placement position of the via hole and the component text mark overlaps (as shown in step 210) ). When it is judged that the placement position of the via hole and the text mark of the component overlaps, it is forbidden to place the via hole at the current position (as shown in step 212), and then correspondingly send a warning message (as shown in step 214), For example, a warning message that the placement pos...
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