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Electronic device, system on chip and method for monitoring data traffic

An electronic device and data technology, applied in the direction of electrical digital data processing, transmission system, digital transmission system, etc., can solve problems such as delay without communication throughput

Inactive Publication Date: 2009-07-15
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For best-effort communication, there is no latency guarantee about communication throughput

Method used

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  • Electronic device, system on chip and method for monitoring data traffic
  • Electronic device, system on chip and method for monitoring data traffic
  • Electronic device, system on chip and method for monitoring data traffic

Examples

Experimental program
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Embodiment Construction

[0035] figure 1A block diagram showing the basic structure of a system-on-chip (or electronic device) with network-on-chip interconnection according to the present invention. A plurality of IP blocks IP1-IP6 are coupled to each other by an on-chip network N. The network NOC comprises a network interface NI for providing an interface between the IP block IP and the network N on chip. The network on chip N also includes a plurality of routers R1-R5. Network interfaces NI1-NI6 are used to convert information from IP blocks into a protocol that can be processed by the on-chip network N and vice versa. Router R is used to transmit data from one network interface NI to another network interface NI. Communication between network interfaces NI depends not only on the number of routers R between them, but also on the topology of routers R. In custom or irregular topologies, router R can be fully connected, connected in a 2D mesh, connected in a linear array, connected in a torus ,...

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PUM

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Abstract

An electronic device is provided which comprises a plurality of processing units (IPl - IP6; Ml - M4), a network-based interconnect (N) with a plurality of network links (Ll - L6) and a network interface (NI; MNI; DNI) which is associated to at least one of the processing units (IPl - IP6; Ml - M4) and which serves to couple the processing units (IPl - IP6; Ml - M4) to the network-based interconnect (N). The plurality of processing units (IPl - IP6; Ml - M4) communicate among each other via a plurality of communication paths (Cl - C4). At least two communication paths (Cl - C4) are merged along the at least one shared network link (Ll - L6) if a combined bandwidth of the at least two communication paths does not exceed an available bandwidth of the at least one shared network link (L 1 - L6).

Description

technical field [0001] The invention relates to an electronic device, a system on a chip and a method for monitoring data traffic. Background technique [0002] Networks on chips (NOC) have proven to be scalable interconnect structures, especially for possible future solutions for on-chip interconnects between so-called IP blocks (i.e. blocks of intellectual property) For systems on chip. IP blocks are usually on-chip modules with specific functions (such as CPU, memory, digital signal processor, etc.). The IP blocks communicate with each other through the on-chip network. A network on a chip usually consists of network interfaces and routers. The network interface is used to provide an interface between the IP block and the on-chip network, that is, the network interface converts information from the IP block into information understandable by the on-chip network, and vice versa. Routers are used to transfer data from one network interface to another. For best-effort c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56G06F13/00
CPCH04L12/2602H04J3/14H04L43/00H04L43/026
Inventor 吉斯·G·W·古森斯卡林·乔尔达什安德雷·勒杜列斯库
Owner NXP BV