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Digital programmable time delay apparatus based on dynamic current mirror

A technology of programming time and dynamic current, applied in the direction of electrical components, pulse processing, single output arrangement, etc., can solve the problems of large static and dynamic power consumption, no way to compare CSIDPDE, monotony, etc., and achieve improved work delay and predictability The effect of improving and saving energy

Active Publication Date: 2011-08-17
智毅聚芯微电子技术(天津)有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Representative works include a current mirror-based CSI DPDE proposed by Mohammad Maymandi-Nejad and Manoj Sachdev. (See references M.Maymandi-Nejad and M.Sachdev, "A digitally programmable delay element, Design and analysis" IEEE Trans.On VeryLarge Scale Integration (VLSI) Systems, Vol.11, No.5, Oct.2003). Although the DPDE proposed by MohammadMaymandi-Nejad can obtain monotonicity, it has a big disadvantage: the static and dynamic power consumption it consumes Too big to compare with traditional CSI DPDE

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  • Digital programmable time delay apparatus based on dynamic current mirror
  • Digital programmable time delay apparatus based on dynamic current mirror
  • Digital programmable time delay apparatus based on dynamic current mirror

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Embodiment Construction

[0022] The technical scheme that the present invention solves its technical problem is: the time delay unit based on the dynamic current mirror that the present invention proposes, such as Figure 3 Show. The DPDE of the present invention uses a switching current mirror to turn off the quiescent current, and separates the control voltages of the two output transistors, so as to avoid short-circuit current consumption when the output terminals PMOS and NMOS of the delay unit are turned on at the same time.

[0023] The working principle of DPDE is simple. When Din is low level, the unit is in the reset state, M2, M3 open Dout is 0 level. When Din goes high, M1 turns on M3, and the gate capacitance of M4 starts to discharge. The speed of discharge is controlled by the current I of Mn1 (Mn2). This current is the sum of the control currents through Msc. The control current is provided by Mp0 ~ Mp3.

[0024] The invention consists of a control part, a dynamic current mirror (a...

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Abstract

The invention relates to a digital programmable time delay device belonging to the technical field of digital time delay circuits on the basis of a dynamic current mirror. The invention is characterized in that the digital programmable time delay device is formed by the sequential and serial connection of a digital control circuit and a time delay circuit, wherein, the time delay circuit adopts the dynamic current mirror to respectively control and output gate voltages of two MOS tubes of an inverter, thereby the power consumption can be reduced while the monotonicity of a transfer function is kept.

Description

technical field [0001] The technical field of direct application of "Digital Programmable Time Delay Device (DPDE) based on dynamic current mirror" is the design of low-power VLSI. The proposed circuit is a class of important modules that can be applied to DCO, DLL, ADPLL, microprocessor and memory. Background technique [0002] Communication has always been an area that a country attaches great importance to for several years. This is because modern communication systems have more and more applications in social and natural environments. Due to the wide demand of communication systems, especially in the fields of military, national security, medical treatment and environmental observation, cost reduction has become an important issue that people are concerned about. With the continuous development of CMOS technology, the voltage, cost and power consumption of digital circuits are also continuously reduced, and the speed is also increased. [0003] In general communicatio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/13H03K5/131H03K5/134
Inventor 克兵格・赛客帝・玻梅杨华中
Owner 智毅聚芯微电子技术(天津)有限公司