Multiprocessor interface with dynamic duty management ability and its program loading/unloading method

Abstract

A multi-processor interface with dynamic work managing capacity and a program unloading method are provided. The method is suitable for use in the microprocessor unit configuration (Micro Processor Unit, MPU) and digital signal processors (Digital Signal Processor, DSP) between communication interface and dynamic management microprocessor unit assigned to the digital signal processor to deal with the work. First of all, the search for digital signal processors in the implementation of the idle unit, then the above-mentioned work of one of a number of threads to the execution unit scheduled for the final implementation of the unit to start this thread to perform. Accordingly, the hardware cost can be saved, the effective multi-core processors to enhance the effectiveness of communication.

Description

technical field [0001] The invention relates to a multiprocessor interface with dynamic work management capability and a program loading and unloading method thereof. Background technique [0002] Due to the vigorous development of communication and multimedia applications, the tasks supported by various electronic products on the market tend to be diversified, which also causes the complexity of calculations of the electronic products to increase significantly when processing these tasks. Taking the most common mobile phone at present as an example, in addition to basic communication functions, it also includes functions such as integrating a digital camera, multimedia player, and even a global positioning system (Global Positioning System, GPS). [0003] In order to be able to cope with such high computing demands while maintaining a certain degree of product upgrade flexibility, a dual-core or multi-core heterogeneous integrated processor has been generally accepted as an...

AI Technical Summary

Problems solved by technology

[0010] 2. In order to process a large number of data streams, DSP places a relatively large number of registers (registers), but its built-in data memory (data memory) does not have the abstraction level of cache (cache) for the purpose of predictive execution. Such a design structure will lead to a significant increase in the cost of context switching

[0011] 3. DSP usually has special-purpose functional modules, such as bit-manipulation unit, Galois-field arithmetic unit, etc., so that the high-cost processor executes the simple The logic operation is relatively wasteful

However, the disadvantage of this method is the cost of an additional set of registers

Images