Method for generating display image signals and display image signal generator
A technology of image signal and generation method, applied in static indicators, instruments, etc., can solve the problems of complex implementation process, increased hardware cost, high read and write speed requirements, etc., to achieve simple algorithm, reduced data volume, and reduced cost. Effect
Inactive Publication Date: 2011-02-09
MUDAN SHIYUAN ELECTRONICS BEIJING
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Usually when the data synchronized with the scanning signal is generated for encoding by the encoder, the data read and write speed is required to be high, and the data read and write speed of the large-capacity memory cannot meet the requirements, so it is necessary to use a buffer (such as a dynamic memory sdram) To increase the speed, this not only increases the hardware cost, but also makes the implementation process complicated
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[0026] The method for generating the image signal of the display of the present invention will be further described below in conjunction with the accompanying drawings of the specification.
[0027] figure 1 It is the circuit block diagram of the display image signal generator of the present invention, in which:
[0028] 1. Controller:
[0029] The controller chooses FPGA (Field-Programmable Gate Array) of XILINX Company, the model is XC3S500E-4PQ208C.
[0030] The controller completes the following tasks:
[0031] (1) Receive the interrupt signal of the keyboard and read the key value to determine the signal format and image to be output currently;
[0032] (2) The signal format and image determined by (1) go to the memory to read the corresponding data;
[0033] (3) Generate scan signals based on the data read in (2);
[0034] (4) Generate 24-bit RGB (Red, Green, Blue) signals according to the algorithm, and output them to the DVI encoder and DAC converter;
[0035] (5) Control the LCD pa...
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The invention discloses a method for generating display image signals, which comprises the following steps: dividing a frame of display image into a plurality of rows and a plurality of lists of rectangular grids, and storing the grid row sequence number and grid list sequence number of all grids, row boundary addresses and list boundary addresses of pixels in the grids and a data value of one pixel in the grids; when the signals of the frame of display image are output, comparing the signal row where the pixel is positioned and the pixel row boundary address of the grids to determine which grid row the current pixel is positioned, and then comparing the signal list where the pixel is positioned and the pixel list boundary address of the grids to determine which grid list the current pixel is positioned so as to acquire the row and list sequence numbers of the grids; and using the pixel data value of the grids according with the row sequence number and the list sequence number as pixel data of the signal row and the signal list. In the method for generating the display image signals, because the data are compressed and one grid only needs to store the data value of one pixel, the data amount is greatly reduced, the algorithm is simple, and the cost is greatly lowered. The invention also discloses a display image signal generator.
Description
Technical field [0001] The invention relates to an electronic display system, in particular to a method for generating a display image signal and a display image signal generator. Background technique [0002] Current display image signal generation methods and generators generally store data according to all pixels of a frame of image, and the data storage capacity is very large. In this way, the data volume of a frame of image needs to be calculated in megabytes, and a signal generator needs a large-capacity memory. To store these data, such as CF card, U disk, etc. Generally, when generating data synchronized with the scan signal for encoder encoding, the read and write speed of the data is relatively high, and the read and write speed of the large-capacity memory cannot meet the requirements, so it is necessary to use a buffer (such as dynamic memory sdram) To increase the speed, this not only increases the hardware cost, but also complicates the implementation process. Sum...
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IPC IPC(8): G09G3/20G09G3/36
Inventor 武晓光杨堃
Owner MUDAN SHIYUAN ELECTRONICS BEIJING