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Method for regulating width of spacer wall and method for etching in construction of spacer wall

A technology for adjusting gaps and spacers. It is used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., and can solve the problems of top loss and increased loss of polysilicon structures.

Active Publication Date: 2012-06-13
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But this also brings a series of side effects, such as the loss of the top of the polysilicon structure, and this loss will increase with the increase of the etching process time

Method used

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  • Method for regulating width of spacer wall and method for etching in construction of spacer wall
  • Method for regulating width of spacer wall and method for etching in construction of spacer wall
  • Method for regulating width of spacer wall and method for etching in construction of spacer wall

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Embodiment Construction

[0023] In the prior art, the width of the spacer is controlled by changing the time of the etching process when the film deposition thickness is constant. The solution of the embodiment of the present invention is to add a step before the formal etching process to adjust the film deposition thickness on the wafer surface, so as to achieve the purpose of finally changing the width of the partition wall.

[0024] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further elaborated below in conjunction with the accompanying drawings. Figure 4 Shown is a schematic diagram of the etching process principle of the embodiment of the present invention. The etching object of the embodiment of the present invention is a wafer made of a single crystal silicon substrate and a polycrystalline silicon structure on the surface of the substrate. The etching process is as follows: Figure 5 shown, including the follo...

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Abstract

The invention discloses a method for regulating width of spacer wall. The component of the spacer wall is silicon oxide and is located on a wafer composed of a single-crystalline silicon substrate and a polycrystalline silicon structure covered on the surface of the single-crystalline silicon substrate, after depositing a silicon oxide film of certain thickness on the surface of the wafer and before carrying out directional etching technique for construction of the spacer wall on the wafer, the following step is carried out: adopting isotropous etching mode to cut the thickness of the siliconoxide film on the surface of the wafer, so that the thickness of the silicon oxide film can achieve the predetermined value. The invention also discloses a method for etching in construction of spacer wall. The scheme in the invention can control the width of the spacer wall and vastly reduce the loss of the top of the polycrystalline silicon structure.

Description

technical field [0001] The invention relates to the technical field of integrated circuit processing and manufacturing, in particular to a method for adjusting the width of a spacer wall and an etching method for constructing a spacer wall. Background technique [0002] The etching process used to construct a silicon oxide-silicon nitride (ON) spacer, the etching object is a wafer composed of a single crystal silicon substrate and a polycrystalline silicon structure on the surface of the substrate. The etching process includes: [0003] Depositing a layer of silicon nitride film on the surface of the wafer; then depositing a layer of silicon oxide film on the silicon nitride film; [0004] Directional etching is performed on the surface of the wafer in the vertical direction for the silicon oxide film until the width of the spacer reaches the required width. [0005] The width of the traditional ON spacer is controlled by the thickness of the silicon oxide film deposited on...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311H01L21/28
Inventor 杜姗姗韩秋华
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP