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Apparatus, processor, system and method for extending cache coherence protocols to support locally buffered data

A cache and cache line technology, applied in memory systems, electrical digital data processing, transaction processing, etc., can solve the problems of increasing processor cost and complexity, slowing down the transaction submission process, etc.

Inactive Publication Date: 2017-07-11
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, adding a separate buffer may increase the cost and complexity of the processor and slow down the transaction commit process

Method used

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  • Apparatus, processor, system and method for extending cache coherence protocols to support locally buffered data
  • Apparatus, processor, system and method for extending cache coherence protocols to support locally buffered data
  • Apparatus, processor, system and method for extending cache coherence protocols to support locally buffered data

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Embodiment Construction

[0018] In the following description, many specific details are set forth, such as specific hardware structures used for transaction execution, specific types and implementations of access monitors, specific cache implementations, specific types of cache coherency models, specific data Granularity and specific types of memory accesses and locations are examples in order to provide a thorough understanding of the invention. It will be apparent, however, to those skilled in the art that these specific details may be practiced without employing the present invention. In other instances, well-known components or methods such as coding in the form of transactional software, demarcation of transactions, specific and alternative multi-core and multi-threaded processor architectures, specific compiler methods / implementations, and specific operational details of microprocessors are not detailed description so as not to unnecessarily obscure the invention.

[0019] The methods and appar...

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PUM

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Abstract

The present invention, entitled Extending Cache Coherency Protocol to Support Locally Buffered Data, describes methods and apparatus for extending cache coherency to preserve buffered data to support transaction execution. Transactional storage operations that reference addresses associated with data items are performed in a buffered manner. Here, the coherency state associated with the cache line holding the data item transitions to the buffer state. In response to local requests for buffered data items, data items are provided to ensure internal transaction order ordering. However, in response to external access requests, a miss response is provided to ensure that transactionally updated data items are not made globally visible until committed. After committing, the buffered line transitions to the modified state to make the data item globally visible.

Description

technical field [0001] The present invention relates to the field of processor execution, and in particular, to the execution of groups of instructions. Background technique [0002] Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that can reside on an integrated circuit device. Consequently, computer system configurations have evolved from single or multiple integrated circuits in the system to the presence of multiple cores and multiple logical processors on individual integrated circuits. A processor or integrated circuit generally includes a single processor die, where a processor die may include any number of cores or logical processors. [0003] The ever-increasing number of cores and logical processors on integrated circuits allows more software threads to execute simultaneously. However, the increase in the number of software threads that can execute simultaneously creates problems related to synchronizing d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/46G06F9/38
CPCG06F12/0831G06F12/084G06F9/467G06F9/3834
Inventor G·希菲尔S·赖金V·巴辛E·科亨O·马古利斯R·萨德
Owner INTEL CORP