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Main device for Ethernet system and relevant clock synchronization method thereof

A technology for network system and clock synchronization, which is used in transmission systems, synchronization devices, digital transmission systems, etc.

Active Publication Date: 2013-05-22
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In short, under the conventional asymmetric mechanism, the master device will not be able to synchronize with the clock of the slave device after waking up because it enters the quiet mode for a period of time. Error in receiving data from the device

Method used

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  • Main device for Ethernet system and relevant clock synchronization method thereof
  • Main device for Ethernet system and relevant clock synchronization method thereof
  • Main device for Ethernet system and relevant clock synchronization method thereof

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Experimental program
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Embodiment Construction

[0047] The Ethernet system 10 adopts a loop timing system (Loop Timing), and the clock recovery is performed by the slave device 120 according to the received signal. For example, the transmitter 111 of the master device 110 uses a free running clock (Free Running Clock) to transmit signals. After the receiver 122 of the slave device 120 receives the transmission signal, the slave device 120 performs a clock recovery (Timing Recovery) operation to generate a recovered clock identical to the free-running clock of the master device 110, the transmitter 121 and the receiver 122 transmits or samples signals according to the recovered clock, respectively. When the receiver 111 receives the signal transmitted by the slave device 120 according to the recovered clock, the receiver 111 performs synchronization so that the clock of the receiver 111 is the same as the recovered clock.

[0048] Please refer to figure 2 , figure 2 It is a schematic diagram of a master device 20 used i...

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Abstract

The invention relates to a main device for an Ethernet system, which contains a receiver, a register, a phase locked loop unit and a transmitter, wherein the receiver is used for generating phase adjustment data according to data transmitted by an assistant device, and the data transmitted by the assistant device contains the phase information of a recovery clock of the assistant device; the register is coupled to the receiver and is used for adding up the phase adjustment data so as to output a phase adjustment value; the phase locked loop unit is coupled to the register and is used for adjusting the phase of an output clock according to the phase adjustment value so as to enable the phase of the output clock and the phase of the recovery clock to maintain a fixed phase difference; and the transmitter is used for transmitting initial data to the assistant device according to the output clock when the main device is revived from a silent mode.

Description

technical field [0001] The present invention relates to a main device and its related clock synchronization method, in particular to a main device and its related clock synchronization method used in an Ethernet system. Background technique [0002] In a Giga Ethernet system, whether there is data transmission or not, the master device (Master) and the slave device (Slave) must maintain clock synchronization by transmitting an idle sequence (Idle Sequence). However, continuously transmitting the idle sequence in the absence of data transmission results in excessive power consumption. Therefore, the Institute of Electrical and Electronics Engineers (IEEE) has formulated the specification of Energy Efficient Ethernet (EEE) to save power consumption. Under the Energy Efficiency Ethernet specification, when the master and slave devices are not transmitting data, both devices enter sleep mode, only occasionally waking up to transmit idle sequences to maintain synchronization. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L7/033
Inventor 俞丁发黄亮维张荣仁李明哲
Owner REALTEK SEMICON CORP
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