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Predecode Repair Cache for Instructions that Cross Instruction Cache Lines

A cache and memory line technology, applied in the field of pre-decoding information, which can solve the problems of increasing the complexity of the pre-decoding function, affecting performance and power utilization, etc.

Inactive Publication Date: 2014-10-08
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For instructions that span two cache lines, both parts of the instruction must be fetched in order to properly predecode the instruction, which increases the complexity of the predecode function and can impact performance and power utilization

Method used

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  • Predecode Repair Cache for Instructions that Cross Instruction Cache Lines
  • Predecode Repair Cache for Instructions that Cross Instruction Cache Lines
  • Predecode Repair Cache for Instructions that Cross Instruction Cache Lines

Examples

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Embodiment Construction

[0017] The present invention will now be described more fully with reference to the accompanying drawings, in which several embodiments of the invention are shown. However, this invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0018] Computer program code or "program code" for being manipulated and for performing operations in accordance with the teachings of the present invention may be available, for example, in C, C++, JAVA Smalltalk, JavaScript Visual Basic High-level programming languages ​​such as TSQL, Perl or written in various other programming languages. Programs for the target processor architecture can also be written directly in native assembler language. Native assembler programs use mnemonic representations of machi...

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PUM

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Abstract

A predecode repair cache is described in a processor capable of fetching and executing variable length instructions having instructions of at least two lengths which may be mixed in a program. An instruction cache is operable to store in an instruction cache line instructions having at least a first length and a second length, the second length longer than the first length. A predecoder is operable to predecode instructions fetched from the instruction cache that have invalid predecode information to form repaired predecode information. A predecode repair cache is operable to store the repaired predecode information associated with instructions of the second length that span across two cache lines in the instruction cache. Methods for filling the predecode repair cache and for executing an instruction that spans across two cache lines arc also described.

Description

technical field [0001] The present invention relates generally to techniques for improving efficiency in processors that process instructions of various lengths, and more particularly to methods for storing in a predecode repair cache An advantageous technique for predecoding information of instructions of a memory line. Background technique [0002] Many processors support instruction groups with variable length instructions. For example, a processor's instruction set may consist of 32-bit instructions and 16-bit instructions. Processors may also have a hierarchical memory configuration with multiple levels of cache including, for example, an instruction cache, a data cache, and a system memory. If the processor also has a deep execution pipeline operating at a high clock rate with pipeline stages of shorter duration, it is also possible that the processor has a pre-decode stage that preprocesses instructions to simplify subsequent decode stages and thus The pipeline is ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
CPCG06F9/382G06F9/3816G06F9/30152
Inventor 罗德尼·韦恩·史密斯布莱恩·迈克尔·斯坦普尔戴维·约翰·曼德扎克詹姆斯·诺里斯·迪芬德尔费尔
Owner QUALCOMM INC