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Memory configuration apparatus and method

A configuration device and configuration method technology, applied in the direction of memory address/allocation/relocation, input/output to record carrier, etc., can solve problems such as poor execution effect

Active Publication Date: 2010-12-15
VIA TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

First, you must make sure that the same way is not configured for both units, otherwise one unit will kick out the other unit that was just configured, which is not good for execution

Method used

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  • Memory configuration apparatus and method

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Embodiment Construction

[0030] In the embodiment of the cache memory described herein, the way specified by the current PLRU vector is allocated to the first functional unit of two functional units (eg, a load unit and a store unit). In this embodiment, the vector bit at the low level of the PLRU tree is also toggled, and the way specified by the toggled vector is allocated to the second functional unit of the two functional units. This embodiment also generates a new PLRU vector based on the above switching vector, which is fast and scalable to a design including a large number of ways.

[0031] Such as figure 1 as shown, figure 1 A block diagram of a microprocessor 100 is illustrated. The microprocessor 100 includes: an instruction cache (instruction cache) 102, an instruction decoder (instruction decoder) 108, a register alias table (register alias table, RAT) 134, a reservation station (reservation stations) 136, a register set (register set) ) 162, a reorder buffer (recorder buffer, ROB) 152,...

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Abstract

The invention relates to a memory configuration apparatus and the method thereof. The memory configuration apparatus is suitable for configuring projects in set association type cache memory, and comprises an array which can provide a first RLRU vector according to a first configuration request from a first function unit; the first RLRU assigns a first project from a cache memory set which is assigned by the first configuration request; the first PLRU vector is a bit tree containing a plurality of layers; a reversing logic unit receives the first PLRU vector and reverses a plurality of established bits, and generate a second PLRU vector according to the second configuration request of a second function unit; the second configuration configure request and the first configuration request are generated at the same time; the same set of the cache memory is assigned by the first configuration request; a second project assigned by the second PLRU vector is different from the first project from the same set; and the established bits include all the bits in the multi-layer bit tree.

Description

technical field [0001] The present invention relates to the field of cache memory, and in particular to the configuration of items of cache memory. Background technique [0002] When a unit (for example: load unit (load unit) or storage unit (store unit)), misses (miss) in the set-associative (set-associative) cache (cache), it from the above One of the ways (way) of the set selected in the cache is configured (allocate) an item (entry). The above cache configuration is a way specified by a vector specifying a replacement scheme, and the vector is usually a pseudo-least recently used (PLRU, PLRU for short) vector. The above-mentioned cache must update the PLRU vector, otherwise, the next time the cache is configured, it will be configured to the same way. Sometimes, two units (eg, a load unit and a store unit) both miss in the cache, and the configuration is initialized at the same time. In this case there are three issues that must be resolved. First, it must be ensured...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/12G06F3/06
Inventor 柯林·艾迪罗德尼·E·虎克
Owner VIA TECH INC
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