Common mode error calibrating circuit of charge coupled pipeline analog-to-digital converter (ADC)

Abstract

The invention provides a circuit for calibrating a common mode error in a charge coupled pipeline analog-to-digital converter (ADC), which comprises a common mode error detecting module, an error quantizing module, an error correcting module and a controller module. The common mode error calibrating circuit can automatically detect the common mode error caused by non-ideal characteristics in the charge coupled pipeline ADC with a fully differential structure and calibrate the common mode error, and the influence of the common mode error is controlled in the minimum resolution requirement of the ADC to solve the problem of accuracy limitation to the current charge coupled pipeline ADC by the common mode error caused by the process variation, thereby further improving the conversion accuracy of the current charge coupled pipeline ADC.

Description

Technical field [0001] The invention relates to a calibration realization circuit for the non-ideal characteristics of a pipeline analog-to-digital converter, in particular to a calibration circuit for common mode errors in a charge-coupled pipeline analog-to-digital converter. Background technique [0002] With the continuous development of digital signal processing technology, the digitization and integration of electronic systems is an inevitable trend. However, the signals in reality are mostly continuously changing analog quantities, which need to be converted into digital signals before they can be input into the digital system for processing and control. Therefore, the analog-to-digital converter is indispensable in the design of future digital systems. made of. In applications such as broadband communications, digital high-definition television, and radar, the system requires the analog-to-digital converter to have a very high sampling rate and resolution at the same tim...

AI Technical Summary

Problems solved by technology

For a charge-coupled pipeline ADC with an accuracy of more than 10 bits, the common-mode error caused by the existing process conditions cannot be ignored

Assume that when the remaining charge packets processed by the previous charge-coupled sub-stage pipeline circuit are transmitted to the next-stage charge-coupled sub-stage pipeline circuit, there is a ΔQcm difference between the common-mode charges of the two-stage charge-coupled sub-stage pipeline circuits, Then the initial potential difference between the charge transfer nodes when the charge transfer starts will change accordingly, and the change of the potential difference will affect the transfer efficiency and speed of the charge packet, thus causing charge transfer errors

Therefore, in order to realize a high-precision charge-coupled pipeline analog-to-digital converter with a fully differential structure with an accuracy of more than 10 bits, it is necessary to provide a circuit for calibrating common-mode errors in its positive and negative signal processing paths to overcome various non-ideal characteristics. The limitation of the common-mode error on the dynamic performance of the charge-coupled pipeline analog-to-digital converter

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