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Grid array shifting buffer memory

A shift register, gate technology, applied in instruments, static indicators, etc., can solve the problems of low display quality, inability to get enough rest, damage to the display device, etc., to reduce the probability of operating characteristics change, and circuit stability. The effect of increasing and decreasing the time of forward bias

Active Publication Date: 2012-10-24
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the potential pull-down of the current gate array drive (GOA) technology is controlled by two sets of signals in turn, and the duty cycle is 50%.
Under such conditions, the transistors responsible for the pull-down potential will be in a positive voltage state for a long time and cannot be fully rested, which will rapidly reduce the reliability of these transistors and directly cause a decrease in display quality or even damage to the display device

Method used

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Examples

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Embodiment Construction

[0037] The following will illustrate the gate array shift register developed in this case to improve the lack of existing means with the aid of figures. like figure 1 Shown is a partial circuit block diagram of the gate array shift register circuit. figure 1 The disclosed gate array shift register circuit 100 is suitable for gate driving circuits of various flat panel displays (such as liquid crystal displays), so as to sequentially drive the gate lines of the flat panel displays. The gate array shift register circuit 100 includes a plurality of gate array shift registers coupled in cascade, such as gate array shift registers SR(n) and SR(n+1). Among them, each gate array shift register (such as: SR(n) or SR(n+1)) receives the front electrode input pulse signal (such as: ST(n-1) or ST(n)), and Sequentially generate the corresponding output pulse signal (eg: G(n) or G(n+1)). And the output pulse signal generated by each gate array shift register is transmitted to the next st...

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Abstract

The invention relates to a grid array shifting buffer memory of a thin film transistor liquid crystal display, which comprises a signal input unit, a control transistor and more than three stabilizing modules, wherein the signal input unit receives and supplies preceding stage input signals; the control end of the control transistor is electrically coupled with the signal input unit and is used for receiving the preceding stage input signals; the control transistor outputs the corresponding output signal on the output end of the shifting buffer memory according to the preceding stage input signals; and the stabilizing modules are electrically coupled to the control end of the control transistor and the output end of the shifting buffer memory so as to stabilize the corresponding output signal generated by the control transistor.

Description

【Technical field】 [0001] The present invention relates to a gate array shift register, and in particular to a gate array shift register with more than three stable modules. 【Background technique】 [0002] In recent years, with the progress of science and technology, the flat liquid crystal display has been popularized gradually, and it has advantages such as lightness and thinness. At present, the driving circuit of the flat liquid crystal display is mainly composed of ICs connected outside the panel, but this method cannot reduce the cost of the product, nor can it make the panel thinner. [0003] Therefore, in the manufacturing process of the driving circuit, the gate driving circuit is directly fabricated on the array substrate instead of the driving chip fabricated by an externally connected IC. The application of this kind of gate array drive (Gate On Array, GOA) technology can be done directly around the panel, reducing the production process, reducing product costs a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/20
Inventor 王柏凯黄俊豪彭中宏
Owner AU OPTRONICS CORP