Pipeline time digital converter

Abstract

The present invention relates to a pipeline time digital converter, comprising a plurality of time digital converting units which are serially connected. Each time digital converting unit comprises a delay unit, an output unit and a measuring unit. The delay unit receives a first clock signal and a first reference signal output by a preceding stage of time digital converting unit. The delay unit generates a plurality of sampling phases between a triggering edge of the first reference signal and a triggering edge of the first clock signal, and performs sampling for the first clock signal according to the sampling phases to obtain a plurality of sampling values. The output unit calculates the sampling values and outputs a converting value. The measuring unit analyzes a time residual value according to the sampling value and the sampling phases, and outputs the time residual value to the next stage of time digital converting unit.

Description

technical field [0001] The present invention relates to a Time-to-Digital Converter (TDC), and more particularly to a pipelined Time-to-Digital Converter (TDC). . Background technique [0002] The time-to-digital converter is one of the important technologies in the development of integrated circuits in recent years, because it is widely used in chips such as communication, biomedicine, and measurement. For example, using a time-to-digital converter with a higher resolution in the Digital Phase-Locked Loop (DPLL) of a communication chip can reduce the phase noise (In-Band Phase Noise) within the loop bandwidth. . If the phase noise is to be lower than 100dBc / Hz, its resolution will need to be as high as 6ps. However, designing a high-resolution time-to-digital converter is a challenge. [0003] Currently, high-resolution time-to-digital converters mainly face three problems: (1) Is the resolution of advanced process circuits high enough? (2) Can the dynamic range (Dynam...

AI Technical Summary

Problems solved by technology

[0003] Currently, high-resolution time-to-digital converters mainly face three problems: (1) Is the resolution of advanced process circuits high enough? (2) Can the dynamic range (Dynamic-Range) of circuit operation be increased? (3) Can complex methods or ultra-high-speed clocks be used to process data? Therefore, a trade-off must be made between the three to meet the system application and power requirements

However, the disadvantage of this architecture is that if the dynamic range of circuit operation is increased, that is, the frequency of the high-speed clock is reduced, multiple high-speed clocks will not be able to use multiple high-speed clocks to produce differences, and its resolution will also be reduced.

Images