Time synchronization method, device and system in transmission system
A technology of time synchronization and transmission system, applied in the field of communication, can solve problems such as inability to achieve synchronization
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Embodiment 1
[0070] This embodiment implements time synchronization by looping back at the line interface side.
[0071] The scheme system block diagram is as follows Figure 4 Shown is the multi-pair transmission scenario.
[0072] ●CO and CPE each contain an equal number of DSL ports, and each port is bundled together through multi-pair technology to provide higher user access rates.
[0073] ●The multi-pair transmission technology can be bongding, vectoring, or MIMO.
[0074] ●△t1, △t2, △t3, △t4, △t5 are respectively in the downlink direction: CO sending digital delay, CO sending analog delay, twisted pair downlink line delay, CPE receiving analog delay, CPE receiving Digital delay.
[0075] ●△t1', △t2', △t3', △t4', △t5' are respectively in the upstream direction: CO receiving digital delay, CO receiving analog delay, twisted pair upstream line delay, CPE sending analog Delay, CPE sending digital delay.
[0076] ●The loopback unit is located at the line interface on the CPE side, a...
Embodiment 2
[0106] This embodiment implements time synchronization by looping back at the analog circuit side.
[0107] The scheme system block diagram is as follows Figure 5 Shown is the multi-pair transmission scenario.
[0108] ●CO and CPE each contain an equal number of DSL ports, and each port is bundled together through multi-pair technology to provide higher user access rates.
[0109] ●The multi-pair transmission technology can be bongding, vectoring, or MIMO.
[0110] ●△t1, △t2, △t3, △t4, △t5 are respectively in the downlink direction: CO sending digital delay, CO sending analog delay, twisted pair downlink line delay, CPE receiving analog delay, CPE receiving Digital delay.
[0111] ●△t1', △t2', △t3', △t4', △t5' are respectively in the upstream direction: CO receiving digital delay, CO receiving analog delay, twisted pair upstream line delay, CPE sending analog Delay, CPE sending digital delay.
[0112] ●The loopback unit is located on the analog circuit side of the CPE si...
Embodiment 3
[0139] This embodiment implements time synchronization by looping back at the digital circuit side.
[0140] The scheme system block diagram is as follows Figure 6 Shown is the multi-pair transmission scenario.
[0141] ●CO and CPE each contain an equal number of DSL ports, and each port is bundled together through multi-pair technology to provide higher user access rates.
[0142] ●The multi-pair transmission technology can be bongding, vectoring, or MIMO.
[0143] ●△t1, △t2, △t3, △t4, △t5 are respectively in the downlink direction: CO sending digital delay, CO sending analog delay, twisted pair downlink line delay, CPE receiving analog delay, CPE receiving Digital delay.
[0144] ●△t1', △t2', △t3', △t4', △t5' are respectively in the upstream direction: CO receiving digital delay, CO receiving analog delay, twisted pair upstream line delay, CPE sending analog Delay, CPE sending digital delay.
[0145] ●The loopback unit is located at the digital circuit side of the CPE ...
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