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Nonvolatile memory control device and multi-stage rearranging method thereof

A reordering and non-volatile technology, applied in the field of non-volatile memory access, can solve problems such as failure to respond to host access requests, time-consuming, data access failures, etc.

Active Publication Date: 2013-04-24
ASOLID TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, because the aforementioned operation of copying the data of the physical block address PBA0 to the physical block address PBA1 (PBA0->PBA1) will cause the memory device to be in a busy state and unable to respond to the access request of the host (host), therefore Generally, the normative standards of non-volatile memory will define the maximum time that the non-volatile memory device is in the busy state (namely, the rated busy period)
Although the existing flash memory access method can solve the situation that when data is written, the data write position has been used and cannot be written, but when the amount of data stored in the data block is too large, the data must be reordered. It will take a lot of time, so that the access action of the flash memory cannot be completed within the rated busy period, resulting in data access failure

Method used

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  • Nonvolatile memory control device and multi-stage rearranging method thereof
  • Nonvolatile memory control device and multi-stage rearranging method thereof
  • Nonvolatile memory control device and multi-stage rearranging method thereof

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Embodiment Construction

[0033] Figure 3A ~ Figure 3B It is a schematic diagram of the operation of the non-volatile memory access method of an embodiment of the present invention, please refer to Figure 3A ~ Figure 3B ,exist Figure 3A ~ Figure 3B In the embodiment, the logical block address LBAN can correspond to at most three physical block addresses PBA0-PBA2 at the same time, but it is not limited thereto. Such as Figure 3A As shown, the data W1-W3 are sequentially written into the data block of the physical block address PBA0, wherein when the data W3 is written into the physical block address PBA0, the position of the data block where the data W3 is scheduled to be written has already been Used by data W2. At this time, in order to avoid the waste of time caused by excessively frequent erasing and writing to the non-volatile memory, the data W3 can be stored in another physical block address PBA1 corresponding to the logical block address LBAN (which is a blank physical block address). ...

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Abstract

The invention provides a nonvolatile memory control device and a multi-stage rearranging method thereof. The multi-stage rearranging method comprises the following steps: dividing a memory block corresponding to a logic block address, which is needed to be rearranged, into a plurality of sub-blocks; executing a host computer command in a rated busy deadline; rearranging one of the sub-blocks; andlastly, executing another host computer command in another rated busy deadline and rearranging another sub-block of the sub-blocks.

Description

technical field [0001] The invention relates to an access method of a nonvolatile memory, and in particular to a nonvolatile memory control device and a multi-stage reordering method thereof. Background technique [0002] Flash memory (flash memory) is a programmable (programmable) read only memory (read only memory, ROM), which allows multiple erasing and updating of stored data. This kind of flash memory is widely used in today's electronic products, and is commonly found in memory cards and flash drives as a medium for exchanging data between digital electronic products. [0003] Generally, the flash memory is divided into multiple storage blocks, and each storage block is subdivided into many storage pages with the same capacity. Here, there is a limitation in the flash memory, that is, when updating data in the flash memory, it is necessary to erase the memory block where the address to be updated is located, and then write the new data. enter. However, with the deve...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/06
Inventor 陈孟豪邱文智
Owner ASOLID TECH
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