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Chaotic discrete particle swarm optimization-based network on chip mapping method

A technology of discrete particle swarm and network-on-chip, applied in the field of optimal mapping scheme search process, can solve problems such as unsuitable discrete space search problems, and achieve fast convergence

Inactive Publication Date: 2013-04-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

[0008] Discrete particle swarm optimization is an improved version of the traditional particle swarm optimization algorithm. It inherits the advantages of the traditional particle swarm optimization algorithm such as fast convergence speed, and at the same time overcomes the unsuitability of the traditional particle swarm optimization algorithm to solve discrete space search problems (such as mapping, routing, scheduling, etc.) etc.) Disadvantages

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  • Chaotic discrete particle swarm optimization-based network on chip mapping method
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Embodiment Construction

[0061] The specific implementation of the power consumption and delay-oriented NoC mapping scheme search algorithm based on the discrete chaotic particle swarm optimization algorithm in the present invention is introduced below.

[0062] The mapping process includes two stages: PE selection and network node allocation, such as figure 1 shown. In the first stage, according to the power consumption delay data of tasks on heterogeneous PEs and the average network delay and average power consumption data, the optimal PE selection scheme is obtained by the chaotic discrete particle swarm algorithm. At this time, the high-level application includes a total of 8 tasks: T1-T8, and 6 available PE resources: PE1-PE6. In the second stage, based on the results of the first stage, the chaotic discrete particle swarm algorithm is used to obtain the final mapping result from the PE to the NoC network platform using accurate delay and power consumption parameters.

[0063] The first stage o...

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Abstract

The invention discloses a chaotic discrete particle swarm optimization-based network on chip (NoC) mapping scheme searching algorithm, which is used for solving the non-deterministic polynomial (NP) problem of mapping from a task graph to a NoC platform in NoC designing to make a mapping scheme simultaneously satisfy the designing needs of low power consumption and low time delay. In the algorithm, a mapping process is divided into two stages. In the first stage, a mapping result from the task graph to a processing element (PE) is obtained by utilizing average power consumption / time delay data by a chaotic discrete particle swarm optimization algorithm. In the second stage, the mapping result from the PE to the NoC platform is obtained based on the result obtained by the first stage by utilizing accurate power consumption / time delay data by the chaotic discrete particle swarm optimization algorithm.

Description

technical field [0001] The invention belongs to an integrated circuit chip optimization design method, in particular to an optimal mapping scheme search process from a task graph to an on-chip network platform in on-chip network design. Background technique [0002] With the rapid increase in integrated scale and density of integrated circuits, the pressure on data communication among on-chip processing cores increases, and Network-on-Chip (NoC) becomes an effective, flexible and scalable solution for on-chip communication. In NoC design, how to map from the specific high-level application to the NoC platform is related to many indicators such as system power consumption, delay, and hardware resource requirements. [0003] Through novelty searches and extensive collection of literature, we found that the NoC mapping methods that have been published are as follows: [0004] Reference Jingcao Hu, Marculescu R., Energy-and performance-aware mapping for regular NoC architecture...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 凌翔王雷陈亦欧胡剑浩
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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