Pulse generation circuit and method, reference voltage generation and its driving circuit and method

Abstract

The invention relates to a pulse generating circuit and a generating method thereof, a reference voltage driving circuit and a driving method thereof as well as a reference voltage generating circuit and a generating method thereof. The pulse generating circuit comprises a delay network and a logic unit, wherein a power supply provides a working voltage for the delay network which delays an input signal and generates a delay signal, the delay signal is weakened along with the increase of the voltage of the power supply relative to the delay time of the input signal and is enhanced along with the decrease of the voltage of the power supply; and the logic unit logically calculates the input signal and the delay signal and generates a pulse signal the width of which is the delay time of the delay signal relative to the input signal. By means of the invention, the node of the reference voltage can be prevented from being overcharged or undercharged.

Description

technical field [0001] The invention relates to the field of circuit design, in particular to a pulse generating circuit and method, a reference voltage generating circuit and a driving circuit and method thereof. Background technique [0002] When the word line of the memory is read, a reference voltage is required, such as figure 1 As shown, an existing reference voltage generating circuit includes a compensation circuit 1, a clamping circuit 2 and a driving circuit 3, and the voltage of the reference voltage node Vout1 is the reference voltage. [0003] see figure 1 , the compensation circuit 1 includes an input terminal connected to the first power supply vdda, a control terminal for receiving the first enable signal EN1 and an output terminal for outputting a control voltage. The clamping circuit 2 includes a second transistor 21 (the second transistor 21 is a PMOS transistor), the source of the second transistor 21 is connected to the reference voltage node Vout1 and...

AI Technical Summary

Problems solved by technology

[0007] However, in the above circuit, when the voltage of the first power supply vdda and the voltage of the second power supply vddb are relatively small, the boosting effect of the driving circuit 3 on the voltage of the reference voltage node Vout1 is limited, which will cause the reference voltage node Vout1 to be underdriven (underdriven ); and when the voltage of the first power supply vdda and the voltage of the second power supply vddb are larger, the boosting effect of the driving circuit 3 on the voltage of the reference voltage node Vout1 is very large, and the reference voltage node Vout1 will be overdriven (overdriven)

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