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cache system

A cache and cache technology, applied in memory systems, memory address/allocation/relocation, instruments, etc., can solve problems such as complex cache coherency control

Inactive Publication Date: 2014-10-08
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] As mentioned above, if the main memory is accessed in units of 128 bytes while the line size of the cache memory remains at 64 bytes similarly to DDR2, cache coherency control becomes complicated

Method used

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Embodiment Construction

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0033] A cache system according to an embodiment of the present invention is included in figure 1 In the central processing unit (hereinafter referred to as "CPU") 1 of the computer shown. CPU 1 includes Instruction Unit (IU) 2, Execution Unit (EU) 3, Level 1 Data Cache (L1D$) 4, Level 1 Instruction Cache (L1I$) 5 and Level 2 Cache (L2$) 6.

[0034] exist figure 1 In the configuration shown, the cache system includes a level 1 data cache 4 , a level 1 instruction cache 5 and a level 2 cache 6 . The cache system will store in main memory (not in figure 1 shown in ) is copied to the primary data cache memory 4 and the secondary cache memory 6. By duplicating data in this way, when data stored in one of the cache memories is accessed, the data can be read out from the cache memory instead of the main memory, thereby enabling information to be read out quickly.

[003...

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Abstract

A cache system comprising: a level 1 cache memory configured to input and output data between computing units, the level 1 cache memory comprising multi-port memory units, each of the multi-port memory units comprising: storing A unit that stores unit data having a first data size; a write unit that simultaneously writes a plurality of unit data sequentially input to consecutive positions of the storage unit; and an output unit that reads and outputs the written storage unit unit data of , wherein, when data having a second data size that is an arbitrary multiple of the first data size and divided into unit data is written into the primary cache memory, by writing sequential unit data to a subset of multi-port memory cells, and write other sequential cell data into another subset of multi-port memory cells to store data in different multi-port memory cells.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from prior Japanese Patent Application No. 2010-27111 filed on February 10, 2010, the entire contents of which are hereby incorporated by reference. technical field [0003] Embodiments of the present invention relate to a cache system for storing data used in computing. Background technique [0004] In computer systems, a small amount of fast cache memory is usually provided separately from the main memory. Multiple levels of cache memory are set up to reduce access to main memory in the event of a cache miss. For example, a secondary cache that can be accessed faster than the main memory may be provided between the primary cache and the main memory. [0005] In the related art, a technique of accelerating data transfer with a CPU is implemented by a main memory operating according to a standard called Double Data Rate 2 (DDR2). DDR2 is a technology that uses both ri...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08
CPCG06F12/0886G06F12/0811G06F12/0851G06F12/0853G06F12/08G06F12/1045
Inventor 平野孝仁
Owner FUJITSU LTD