Encapsulation process
A packaging process and packaging colloid technology, which is applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve problems affecting process reliability, poor bonding between wafer carrier and carrier, and improve process reliability. Effect
Active Publication Date: 2013-08-21
ADVANCED SEMICON ENG INC
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Problems solved by technology
[0006] The present invention provides a packaging process, which can avoid the problem of poor bonding between the chip carrier and the carrier due to the use of large-size solder balls when the known stacked semiconductor element packaging is applied to the wafer-level packaging process, which affects the reliability of the process. question
Method used
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Embodiment Construction
[0044] Compared with the known technology, solder balls are first formed on the bottom of the chip carrier, and the chip carrier with solder balls is placed on the carrier, so that the solder balls on the chip carrier are embedded in the adhesive layer on the carrier In the present invention, the semiconductor substrate is bonded to the carrier first, and after the wafer-level packaging process is completed and the semiconductor substrate is separated from the carrier, solder balls are formed on the first surface at the bottom of the semiconductor substrate. A number of examples are listed below to illustrate the process of the present invention.
[0045] Figure 1A ~ 1K A packaging process according to an embodiment of the present invention is shown in sequence.
[0046] First, if Figure 1A As shown, a semiconductor substrate 110 is provided, which is, for example, a common silicon wafer or made of other semiconductor materials. The semiconductor substrate 110 has a first ...
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The invention relates to an encapsulation process. The encapsulation process comprises the following steps of: arranging a semiconductor base material onto a carrier, wherein one side, facing the carrier, of the semiconductor base material is provided with a plurality of connection points; thinning the semiconductor base material by the back side of the semiconductor base material; forming a plurality of through silicon penetrating holes in the thinned semiconductor base material; forming a plurality of first connection pads on the semiconductor base material, wherein the first connection pads are connected with the through silicon penetrating holes respectively; connecting a plurality of chips and the semiconductor base material, wherein the chips are electrically connected with the corresponding first connection pads respectively; forming encapsulation colloid on the semiconductor base material so as to cover the chips and the first connection pads; separating the semiconductor basematerial from the carrier, and forming a plurality of solder balls on the semiconductor base material; and cutting the encapsulation colloid and the semiconductor base material.
Description
technical field [0001] The invention relates to a packaging structure, and in particular to a stacked semiconductor element packaging structure. Background technique [0002] In today's information society, users are pursuing high-speed, high-quality, and multi-functional electronic products. As far as product appearance is concerned, the design of electronic products is moving towards the trend of light, thin, short and small. Therefore, electronic packaging technology has developed multiple semiconductor device packaging technologies such as stacked semiconductor device packaging. [0003] Stacked semiconductor element packaging is to package multiple semiconductor elements in the same package structure by vertical stacking, which can increase the packaging density to make the package miniaturized, and can shorten the signal transmission between semiconductor elements by using three-dimensional stacking The path length can increase the speed of signal transmission betwee...
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IPC IPC(8): H01L21/50H01L21/60
CPCH01L24/97H01L2224/73204
Inventor 王盟仁
Owner ADVANCED SEMICON ENG INC