Light-emitting diode (LED) package structure and packaging method thereof

Abstract

A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.

Description

technical field [0001] This case involves a packaging structure and method, especially a packaging structure and method for light emitting diodes. Background technique [0002] Applying semiconductor manufacturing process to silicon wafer (Si wafer) can not only produce a large number of light-emitting diode substrates (LED submount), but also allow packaging manufacturers to reduce costs, increase production, and achieve better heat dissipation effects. [0003] The technology disclosed in Taiwan Patent No. I331415 is the existing LED packaging technology using semiconductor manufacturing process. Referring to the specification and drawings of this patent case, it can be seen that on the upper and lower surfaces of the silicon substrate covered with an insulating layer, the conductive layer and the electrode connected in the electrode via hole of the silicon substrate are respectively formed first, and then , and then place the chip on the conductive layer on the upper sur...

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Problems solved by technology

[0004] However, the technique disclosed in the preceding patent must be completed by forming a conductive layer and electrodes on the upper and lower surfaces of the silicon substrate, and bonding the conductive layer and electrodes in the electrode via holes. Plating (sputter) technology to form the conductive layer indirectly increases the manufacturer's time and cost

In addition, after actually implementing the technology of the aforementioned patent case, it is also found that the electrical connection between the conductive layer and the electrode in the electrode via hole of the silicon substrate is not ideal, that is to say, the conductive layer and the electrode are not easy to be connected in the silicon substrate. The electrode via hole of the base material is completely bonded, which directly leads to poor luminous effect of the chip and affects the product yield of the manufacturer.

In addition, in the subsequent process of using adhesive tape to seal the electrode via hole and then forming a molding compound, the problem of glue overflow is also prone to occur.

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