Method for rapidly debugging and locating chip functional fault and debugging circuit

A technology for functional failure and circuit debugging, which is applied in electronic circuit testing and other directions, can solve the problems of difficult control of design quality, easily damaged chips, high design cost, etc., and achieve the effect of fast and low-cost debugging and positioning, and realize the effect of debugging and positioning

A technology for functional failure and circuit debugging, which is applied in electronic circuit testing and other directions, can solve the problems of difficult control of design quality, easily damaged chips, high design cost, etc., and achieve the effect of fast and low-cost debugging and positioning, and realize the effect of debugging and positioning

CN102236065AInactive Publication Date: 2011-11-09SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Method for rapidly debugging and locating chip functional fault and debugging circuit
  • Method for rapidly debugging and locating chip functional fault and debugging circuit
  • Method for rapidly debugging and locating chip functional fault and debugging circuit

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Embodiment Construction

[0011] In one embodiment, the method for quickly debugging and locating chip function faults is to embed a debugging circuit inside the chip during design. When the chip malfunctions, input a predefined signal through one or more pins of the chip to make the chip enter the debugging mode; and select the internal signal of the chip to be observed according to the input predefined signal; The selected internal signal of the chip is output through a predefined pin of the chip; by observing the waveform of some internal signal during the working process of the chip, and comparing it with the expected waveform of the signal during design, the debugging and monitoring of functional failures can be realized. position.

[0012] see figure 1 As shown, for example, a high-level signal is input from the IO0 pin of the chip, a clock signal is input from the IO1 pin, and a predefined signal is input from the IO2, IO3, and IO4 pins; among them, the input from the IO4 pin is a serial row d...

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Abstract

The invention discloses a method for realizing rapid debugging and locating of a chip functional fault. The method is characterized by comprising the following steps: embedding a debugging circuit in a chip circuit, inputting a predefined signal by virtue of one or more pins of the chip to ensure the chip to enter into a debugging mode when the chip has the functional fault and selecting the internal signals to be observed of the chip according to the input predefined signal; outputting the selected internal signals of the chip by virtue of one predefined pin of the chip; and realizing the debugging and locating of the functional fault by observing the waveforms of certain internal signals in the working process of the chip and comparing the waveforms with the expected waveforms of the signals during design. The invention also discloses the debugging circuit used in the method. By adopting the method, the debugging and locating of the chip fault can be rapidly realized at low cost after the chip has the functional fault.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a method capable of quickly debugging and locating chip function faults. The invention relates to a debugging circuit in the method. Background technique [0002] The development of the semiconductor process level makes it possible to further increase the integration level of integrated circuits (ICs). The electronics industry has entered the VLSI era from the LSI era. With the maturity of deep submicron process technology, the chip design industry is facing severe problems: due to the development of chip function and The cost is getting higher and higher, the design quality is becoming more and more difficult to control, the probability of design and production problems after chip production is increasing, and the time and labor costs and complexity of troubleshooting are also increasing. When designing 3 metal layers ten years ago, if there is a problem with the chip, you can dire...

Claims

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Application Information

Patent Timeline
09 Nov 2011
Publication
CN102236065A
IPC
G01R31/28
Inventors
舒海军