Multiple Depth Shallow Trench Isolation Process

Abstract

A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer to have areas of predefined depths;—Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and—Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area.

Description

[0001] Related Application Cross Reference [0002] This application claims U.S. Provisional Application No. 61 / 145,354, filed January 16, 2009, entitled "MULTIPLE DEPTH SHALLOW TRENCH ISOLATION WITH A SINGLE CRITICAL MASK AND ETCH STEP PROCESS" , the entirety of which is hereby incorporated by reference. technical field [0003] The present invention relates to a unique process for forming shallow trenches of multiple depths within a die for device isolation. Background technique [0004] Different regions on the semiconductor die include electronic circuits with structures that need to be electrically isolated from other portions of the semiconductor die. For this purpose, trenches are formed around the respective structures. However, some structures require trenches that reach deeper into the substrate to adequately provide insulation, according to the respective specifications. Various methods exist for forming such isolation trenches within semiconductor devices. H...

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Problems solved by technology

However, these conventional methods require further elaboration if trenches with different depths on the same wafer are required

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