Integrated circuit and integrated circuit method

An integrated circuit and voltage technology, which is applied to the circuit field of static random access memory, can solve problems such as the reduction of storage voltage, and achieve the effect of reliable data storage

Active Publication Date: 2013-10-02
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Self-biased diodes suffer from reductions in storage voltage due to critical voltage changes due to process, voltage, and temperature variations

Method used

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  • Integrated circuit and integrated circuit method
  • Integrated circuit and integrated circuit method
  • Integrated circuit and integrated circuit method

Examples

Experimental program
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Embodiment Construction

[0041] Figure 1A An embodiment of an SRAM array 100 including a plurality of SRAM cells 102 is shown. Such as Figure 1A As shown, the SRAM cell is coupled to a high (or positive) voltage supply node V DD and a low (or negative) voltage supply node V SS , the node V SS Can be set to ground. However, the leakage current of the SRAM array 100 in the standard operating state when data is not being read or written causes these conventional SRAM arrays to have high power consumption. Such as Figure 1B As shown, in order to reduce the leakage current and power consumption of the SRAM array, usually at the low voltage supply node V SS And a self-biased diode 104 is coupled between the SRAM array 100 . However, the self-biased diode 104 varies significantly through process, voltage, and temperature, thus creating problems between data retention and optimization of leakage.

[0042] For example, when the self-biased diode 104 is in a non-conducting state, current does not flow ...

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PUM

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Abstract

An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level.

Description

technical field [0001] The present invention relates to integrated circuits. In particular, it relates to circuits of static random access memory (SRAM) on a semiconductor substrate. Background technique [0002] Semiconductor memory devices are continually being designed to be smaller, faster, and require less power to facilitate portable devices using battery power. SRAM is a volatile memory widely used in laptops and personal digital assistants (PDAs), in which each memory cell includes a transistor base bistable latch (transistor -based bistable latch), which is either in the "conducting" state or in the "non-conducting" state. SRAM devices may include a matrix of thousands of individual memory cells fabricated on an integrated circuit chip. [0003] When data is not read or written in the SRAM array in the standard operating state, the leakage current causes the traditional SRAM array to have high power consumption. In order to reduce leakage current and power consu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/4063
CPCG11C5/147G11C11/412G11C11/4063
Inventor 邓儒杰许国原
Owner TAIWAN SEMICON MFG CO LTD
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