Production-line processor device for rapidly disposing prediction error of branch instruction

Abstract

The invention provides a production-line processor device for rapidly disposing a prediction error of a branch instruction. The production-line processor device comprises a production-line processor, a branch prediction unit, a branch result detection unit, a branch instruction fetching redirection unit and a production-line control unit, wherein the production-line processor at least comprises an instruction fetching section, a decoding section, an emission section, an execution section and a retirement section in sequence; the branch prediction unit is used for early predicting a branch direction and a target address; the branch result detection unit is used for computing an actual branch direction and an actual target address, comparing the predicted branch direction and target address which are delivered by the branch prediction unit with the actual branch direction and the actual target address, and judging whether a prediction error of the branch instruction happens or not; the branch instruction fetching redirection unit is used for receiving a detection result and the actual branch target address, and if the prediction error of the branch instruction happens, an instruction fetching member is immediately informed; and the production-line control unit is used for receiving the detection result generated by the branch result detection unit, and if the prediction error of the branch instruction is found, all levels of production lines are controlled to handle the branch prediction error. According to the production-line processor device provided by the invention, the production-line do-nothing operation caused by the prediction error of the branch instruction can be eliminated or greatly reduced and the performance of the production-line processor is improved.

Description

technical field [0001] The invention relates to a pipeline processor, in particular to a pipeline processor device capable of rapidly handling branch instruction prediction errors. technical background [0002] Microprocessors are generally implemented using pipelines, especially for high-performance microprocessors, whose pipelines are divided carefully and have many stages. John Hennessy and David Patterson described the classic five-stage pipeline processor architecture in their book "Computer System Architecture: A Quantitative Research Approach". The five-level pipeline section refers to fetching, decoding, executing, accessing memory, and writing back, respectively. The fetching section is responsible for accessing the instruction memory to obtain instructions; the decoding section is responsible for decoding instructions and preparing operands for instruction execution; the execution section is responsible for instruction execution and obtaining results; The memory a...

AI Technical Summary

Problems solved by technology

[0007] In order to overcome the deficiency that existing pipeline processors have many pipeline empty operations and affect the performance of pipeline processors when encountering branch instruction prediction errors, the present invention provides a method to eliminate or greatly reduce the pipeline empty operation caused by branch instruction prediction errors. Pipeline processor device for quickly handling branch instruction prediction errors to operate and improve pipeline processor performance

Images