Statistical method and device
A statistical method and counter technology, applied in the computer field, can solve the problems of increasing the burden on the processor and reducing the efficiency of counting, and achieve the effect of reducing the burden and improving the efficiency.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0021] The embodiment of the present invention provides a statistical method, see figure 1 , figure 1 It is a flow chart of a statistical method provided by an embodiment of the present invention, and the method includes:
[0022] 101: Execute a first computer instruction.
[0023] During specific implementation, there may be multiple implementation manners for the processor to execute the first computer instruction, which is not specifically limited in the present invention. For example, after the program counter (program counter, PC) calculates the address of the first computer instruction, the address register (Address Register, AR) sends the address of the first computer instruction to the cache (cache) through the address bus. The instruction pipeline fetches the first computer instruction from the cache and sends it to an instruction register (Instruction Register, IR). An instruction decoder (Instruction Decoder, ID) decodes the first computer instruction. The post-...
Embodiment 2
[0051] An embodiment of the present invention provides a statistical device. see Figure 4 , Figure 4 It is a schematic diagram of the statistical device provided by the embodiment of the present invention. The unit includes:
[0052] The execution unit 401 is configured to execute a first computer instruction.
[0053] During specific implementation, there may be multiple implementation manners for the processor to execute the first computer instruction, which is not specifically limited in the present invention. For example, after the PC calculates the address of the first computer instruction, the AR sends the address of the first computer instruction to the cache through the address bus. The instruction pipeline fetches the first computer instruction from the cache and sends it to the IR. The ID decodes the first computer instruction. The post-decoding processor issues various control information needed to execute the first computer instruction through the control c...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 