Semiconductor device and manufacturing method of semiconductor device
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as gate length differences, and achieve the effect of gate length optimization
Active Publication Date: 2012-05-16
SONY CORP
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- Application Information
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Problems solved by technology
In particular, when increasing the effective gate width by raising the fins, the difference in gate length becomes a big problem in processing
Method used
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Embodiment Construction
[0044] In the following, preferred embodiments for realizing the present invention will be described; however, the present invention is not limited to the following examples.
[0045] In addition, description will be made in the following order.
[0046] 1. The semiconductor device of the first embodiment
[0047] 2. The semiconductor device manufacturing method of the first embodiment
[0048] 3. Semiconductor device of the second embodiment
[0049] 4. Semiconductor device manufacturing method of the second embodiment
[0050] 5. The semiconductor device of the third embodiment
[0051] 6. The semiconductor device manufacturing method of the third embodiment
[0052] 7. Semiconductor device (fin type) of the fourth embodiment
[0053] 8. Semiconductor device (fin type) manufacturing method of the fourth embodiment
[0054] 1. The semiconductor device of the first embodiment
[0055] figure 1 is a schematic configuration diagram of the semiconductor device of the fir...
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A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
Description
[0001] Cross References to Related Applications [0002] This application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2010-243251 filed in Japan Patent Office on Oct. 29, 2010, the entire content of which is hereby incorporated by reference. technical field [0003] The present invention relates to a semiconductor device using a metal gate electrode and a method of manufacturing the semiconductor device. Background technique [0004] In the related art, according to Moore's law, the degree of integration of semiconductor devices doubles every 18 to 24 months. However, the gate tunnel leakage current cannot be ignored near the 90nm node, so the thinning of the gate oxide film for MOSFETs has almost completely stopped. In addition, because it is difficult to control the short channel effect (short channel effect), the reduction of the gate length is progressing slowly. [0005] Therefore, it is difficult to improve the perform...
Claims
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IPC IPC(8): H01L27/092H01L29/78H01L29/423H01L21/8238
CPCH01L29/66545H01L21/823814H01L29/4983H01L21/823864H01L29/66553H01L21/823842H01L27/092H01L29/42356H01L21/823828H01L29/41783H01L21/28079H01L21/28088H01L21/28097H01L21/823821H01L21/82385H01L27/0924H01L27/0928H01L29/0649H01L29/0847H01L29/42376H01L29/4958H01L29/4966H01L29/4975H01L29/517H01L29/6656
Inventor 松本光市
Owner SONY CORP