Method for forming grid
A gate and dummy gate technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve problems such as substrate damage
Active Publication Date: 2012-06-06
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
However, in this patent document, the argon (Ar) sputtering process is used to increase the width of the top of the trench, which is easy to cause damage to the substrate
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[0032] The method for forming a gate according to the specific embodiment of the present invention first removes part of the dummy gate and sidewalls, forms a first trench with a width at the top greater than that at the bottom on the dummy gate and sidewalls, and then removes the dummy gate to form A gate trench whose top width is greater than the bottom width. In the present invention, when forming the first trench whose top width is larger than the bottom width, since the dummy gate is not completely removed, the remaining dummy gate plays a role in protecting the semiconductor substrate, so that the semiconductor substrate will not be damaged, so the present invention can be solved. In the prior art, after removing the dummy gate and forming the gate trench, bombarding the dielectric layer around the gate trench to increase the top width of the gate trench will damage the semiconductor substrate.
[0033] In order to enable those skilled in the art to better understand the...
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The invention discloses a method for forming a grid. The method comprises the steps of: providing a semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a forged grid structure in the dielectric layer, wherein the forged grid structure comprises a forged grid and a grid dielectric layer positioned between the semiconductor substrate and the forged grid, and side walls are arranged at the periphery of the forged grid structure; removing part of the forged grid and the side walls, forming a first groove in the forged grid and the side walls, wherein the width of the top part of the first groove is more than that of the bottom part of the first groove; removing the remaining forged grid and forming a grid groove; and filling a grid material into the grid groove and forming the grid. Since the width of the top part of the first groove is more than that of the bottom part of the first groove, the filling of the grid material is benefited, the filling performance of the grid material is improved, and the gap formed in the grid is avoided or at least reduced. In addition, the first groove with the width of the top part being more than that of the bottom part can be formed without damaging the semiconductor substrate.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a gate. Background technique [0002] In the prior art, the process of forming a gate can be divided into a gate first process and a gate last process. The gate-front process refers to first depositing a gate dielectric layer, forming a gate electrode on the gate dielectric layer, then performing source-drain implantation, and then performing an annealing process to activate ions in the source-drain. The process steps of the front-gate process are simple, but during annealing, the gate electrode must inevitably withstand high temperatures, resulting in a shift in the threshold voltage Vt of the MOS tube and affecting the performance of the tube. The gate last process means that after the annealing process, that is, after the high temperature step, the polysilicon dummy gate is etched away to form a dummy gate trench, and then the dummy gate trench ...
Claims
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IPC IPC(8): H01L21/28H01L21/336
Inventor 洪中山李凡
Owner SEMICON MFG INT (SHANGHAI) CORP