Method for forming grid
A gate and dummy gate technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as substrate damage, and achieve the effect of improving filling performance
Active Publication Date: 2014-07-02
SEMICON MFG INT (BEIJING) CORP
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Problems solved by technology
However, in this patent document, the argon (Ar) sputtering process is used to increase the width of the top of the trench, which is easy to cause damage to the substrate
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[0030] In the gate forming method according to the specific embodiment of the present invention, after the dummy gate structure is formed on the semiconductor substrate, the first wet etching with a low selectivity (less than 19) to the dummy gate and sidewalls is used to remove the part The dummy gate and the sidewall around the dummy gate form a first trench on the dummy gate and the sidewall, and the top width of the first trench is larger than the bottom width, and then the dummy gate and the sidewall have a high selectivity The remaining dummy gate is removed by the second wet etching to form a gate trench. The width of the top of the gate trench is naturally greater than the width of the bottom, and then the gate material is filled in the gate trench to form a gate. Since the top width of the formed gate trench is larger than the bottom width, it is beneficial to fill the gate material, improve the filling performance of the gate material, and avoid or at least reduce the...
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The invention provides a method for forming a grid. The method comprises the following steps of: providing a semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a forged grid structure in the dielectric layer, wherein the forged grid structure comprises a forged grid and a grid dielectric layer positioned between the semiconductor substrate and the forged grid, and side walls are arranged at the periphery of the forged grid structure; removing parts of the forged grid and the side walls by using first wet-process etching, forming a first groove in the forged grid and the side walls, wherein the width of the top part of the first groove is more than that of the bottom part of the first groove, and the etching selection ratio of the first wet-process etching for the forged grid and the side walls is less than 19; removing the remaining forged grid by second wet-process etching and forming a grid groove; and filling a grid material into the grid groove and forming the grid. The method contribute to the filling of the grid material, improving the filling performance of the filling material and avoiding or at least reducing the gap in the grid. In addition, the semiconductor substrate can not be damaged.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a gate. Background technique [0002] In the prior art, the gate forming process can be divided into a gate first (gate first) process and a gate last (gate last) process. The gate-front process refers to first depositing a gate dielectric layer, forming a gate electrode on the gate dielectric layer, then performing source-drain implantation, and then performing an annealing process to activate ions in the source-drain. The process steps of the front-gate process are simple, but during annealing, the gate electrode must inevitably withstand high temperatures, resulting in a shift in the threshold voltage Vt of the MOS tube and affecting the performance of the tube. The gate last process means that after the annealing process, that is, after the high temperature step, the polysilicon dummy gate is etched away to form a dummy gate trench, and then th...
Claims
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IPC IPC(8): H01L21/336H01L21/28
Inventor 洪中山李凡
Owner SEMICON MFG INT (BEIJING) CORP