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Double-edge-triggered Gray code counter

A dual-edge trigger and flip-flop technology, applied in the field of counters, can solve the problems of increasing the length of the counting cycle, and achieve the effects of improving counting efficiency, shortening the counting cycle, and high application value

Active Publication Date: 2012-06-13
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] In the above two methods, the first one has a transition state in the converted Gray code because there is a transition state in binary counting, and the second Gray code counter can obtain the Gray code counting result without a transition state, but it can only be used for Counting on a single clock edge increases the length of the counting cycle

Method used

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Embodiment Construction

[0032] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0033] see Figure 1-Figure 6 , first, construct the first latch LATCH1 and the second latch LACHT2. Among them, the first latch LATCH1 reads data when the input clock is low, and latches data when it is high; the second latch LATCH2 reads data when the input clock is high, and latches data when it is low , and both the CLR and RST terminals of the first latch LATCH1 and the second latch LACHT2 are active low. When both the CLR and RST terminals are high level, the first latch LATCH1 and the second latch LACHT2 enter the normal working state, and when CLK is low, the first latch LATCH1 reads the signals of the D and DB terminals (D, DB are mutually inverting signals) and output at Q1 and Q1B terminals, while the output terminal of the second latch LACHT2 remains in the original state; when CLK becomes high level, the output terminal of the fi...

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PUM

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Abstract

The invention discloses a double-edge-triggered Gray code counter. A modulo-N counter is formed by combining N+1 groups of triggers. Each group of trigger mainly comprises two latches with different controlled conditions and an additional logic circuit, and has forward output and backward output, wherein the backward output is a half cycle ahead of the forward output. The first group of trigger outputs the CNT[0]th bit of the counter, the Nth group of trigger outputs the CNT[N-1]th bit of the counter, and the output of the (N+1)th group of trigger serves as the input of the first group of trigger. The input of a second group of trigger is obtained by NOR gate operation over the backward output of the first group of trigger and the CNT[N+1]th bit. The input of an Mth stage is obtained by performing NAND gate operation on the backward output of the CNT[0]th bit and the forward output of the CNT[M-2]th to CNT[1]st bits and on the backward output of the CNT[0]th bit and the backward output of an (N+1)th stage and then performing the NOR gate operation on the output subjected to the NAND gate operation and the backward output of the trigger of an (M-1)th stage.

Description

technical field [0001] The invention relates to a counter in a logic circuit, in particular to a Gray code counter. Background technique [0002] Traditional binary counters have defects in engineering applications. In some fields, such as high-stability engineering control, it is difficult to ensure the stability and uniqueness of counting, because each count of binary counters is accompanied by the flipping of multiple bits. There may be a variety of transition states in the process, and these transition states will increase the uncertainty of the counting result. For example, from 011 to 100, all three bits have been flipped. If there is a deviation in the change time of each bit, it will appear as 000, 101, 110 and other transition states, these transition states will cause serious engineering accidents in industrial control, and when used in traffic lights, it will lead to uncertain changes in traffic lights. [0003] The gray code counter has successfully solved t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K21/00
Inventor 吕坚周云王璐霞廖宝斌熊丽霞
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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